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PDF K6F4016U6G-F Data sheet ( Hoja de datos )

Número de pieza K6F4016U6G-F
Descripción 256Kx16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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K6F4016U6G Family
Preliminary
CMOS SRAM
Document Title
256Kx16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0 Initial Draft
Draft Date
June 11, 2003
Remark
Preliminary
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
- 1 - Revision 0.0
June 2003

1 page




K6F4016U6G-F pdf
K6F4016U6G Family
Preliminary
CMOS SRAM
AC OPERATING CONDITIONS
VTM3)
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL= 100pF+1TTL
CL= 30pF+1TTL
R12)
CL1)
R22)
1. Including scope and jig capacitance
2. R1=3070, R2=3150
3. VTM =2.8V
AC CHARACTERISTICS ( Vcc=2.7~3.3V, Industrial product:TA=-40 to 85°C )
Parameter List
Symbol
Read
Write
Read cycle time
Address access time
Chip select to output
Output enable to valid output
UB, LB Access Time
Chip select to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
UB, LB Valid to End of Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
tRC
tAA
tCO
tOE
tBA
tLZ
tBLZ
tOLZ
tHZ
tBHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
tOW
Speed
55ns
70ns
Min Max Min Max
55 - 70 -
- 55 - 70
- 55 - 70
- 25 - 35
- 55 - 70
10 - 10 -
10 - 10 -
5-5 -
0 20 0 25
0 20 0 25
0 20 0 25
10 - 10 -
55 - 70 -
45 - 60 -
0-0 -
45 - 60 -
45 - 60 -
40 - 50 -
0-0 -
0 20 0 20
25 - 30 -
0-0 -
5-5 -
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Vcc for data retention
VDR
Data retention current
IDR
Data retention set-up time
tSDR
Recovery time
tRDR
1. 1) CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or
2) 0CS20.2V(CS2 controlled)
Test Condition
CS1Vcc-0.2V1), VIN0V
Vcc=1.5V, CS1Vcc-0.2V1), VIN0V
See data retention waveform
Min Typ Max Unit
1.5 - 3.3 V
- - 3 µA
0-
tRC -
- ns
-
- 5 - Revision 0.0
June 2003

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