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PDF K6F1008V2C-YF70 Data sheet ( Hoja de datos )

Número de pieza K6F1008V2C-YF70
Descripción 128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! K6F1008V2C-YF70 Hoja de datos, Descripción, Manual

K6F1008V2C Family
Document Title
128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0 Initial Draft
0.1 Revise
- Changed Package Type
: 48(36)-TBGA-6.00x7.00 to 32-TSOP1-0813.4F
1.0 Finalize
Draft Data
November 27, 2001
December 13, 2001
Remark
Preliminary
Preliminary
June 12, 2002
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 1.0
June 2002

1 page




K6F1008V2C-YF70 pdf
K6F1008V2C Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL= 100pF+1TTL
CL = 30pF+1TTL
VTM3)
R12)
CL1)
R22)
1. Including scope and jig capacitance
2. R1=3070, R2=3150
3. VTM =2.8V
AC CHARACTERISTICS (Vcc=3.0~3.6V, Industrial product:TA=-40 to 85°C)
Parameter List
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Read Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
1. The parameter is measured with 30pF test load.
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
Speed Bins
55ns1)
70ns
Min Max Min Max
55 - 70 -
- 55 - 70
- 55 - 70
- 25 - 35
10 - 10 -
5-5-
0 20 0 25
0 20 0 25
10 - 10 -
55 - 70 -
45 - 60 -
0-0-
45 - 60 -
40 - 50 -
0-0-
0 20 0 20
25 - 30 -
0-0-
5-5-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Vcc for data retention
VDR CS1Vcc-0.2V1)
Data retention current
IDR Vcc=1.5V, CS1Vcc-0.2V1)
Data retention set-up time
Recovery time
tSDR
tRDR
See data retention waveform
1. CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or CS20.2V(CS2 controlled)
Min Typ Max Unit
1.5 - 3.6 V
- - 1.0 µA
0-
tRC -
- ns
-
5 Revision 1.0
June 2002

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