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PDF K4X56163PE-LG Data sheet ( Hoja de datos )

Número de pieza K4X56163PE-LG
Descripción 16M x16 Mobile DDR SDRAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! K4X56163PE-LG Hoja de datos, Descripción, Manual

K4X56163PE-L(F)G
Mobile-DDR SDRAM
16M x16 Mobile DDR SDRAM
FEATURES
• 1.8V power supply, 1.8V I/O power
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• MRS cycle with address key programs
- CAS Latency ( 3 )
- Burst Length ( 2, 4, 8 )
- Burst Type (Sequential & Interleave)
- Partial Self Refresh Type ( Full, 1/2, 1/4 array )
- Internal Temperature Compensated Self Refresh
- Driver strength ( 1, 1/2, 1/4, 1/8 )
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
• Data I/O transactions on both edges of data strobe, DM for masking.
• Edge aligned data output, center aligned data input.
• No DLL; CK to DQS is not synchronized.
• LDM/UDM for write masking only.
• 7.8us auto refresh duty cycle.
• CSP package.
Operating Frequency
Speed @CL3
*CL : CAS Latency
DDR200
100Mhz
DDR133
66Mhz
Column address configuration
Organization
16Mx16
DM is internally loaded to match DQ and DQS identically.
Row Address
A0 ~ A12
Column Address
A0-A8
1 March 2004

1 page




K4X56163PE-LG pdf
K4X56163PE-L(F)G
Power Up Sequence for Mobile DDR SDRAM
Mobile-DDR SDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CK
CK
CKE Hi
CS
RAS
CAS
ADDR
Key Key RAa
BA0
BA1
A10/AP
RAa
DQ Hi-Z Hi-Z
WE
DQM
High level is necessary
tRP tARFC
tARFC
Precharge
(All Bank)
Auto
Refresh
Auto
Refresh
Normal
MRS
Row Active
(A-Bank)
Extended
MRS
Note:
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define PASR or DS operating type of the device after normal MRS.
: Don’t care
EMRS cycle is not mandatory and the EMRS command needs to be issued only when either PASR or DS is used.
The default state without EMRS command issued is half driver strength, and Full array refreshed .
The device is now ready for the operation selected by EMRS.
For operating with PASR or DS, set PASR or DS mode in EMRS setting stage.
In order to adjust another mode in the state of PASR or DS mode, additional EMRS set is required but power up sequence is not needed again at this
time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
5 March 2004

5 Page





K4X56163PE-LG arduino
K4X56163PE-L(F)G
Mobile-DDR SDRAM
Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The
DDR SDRAM has four independent banks, so two Bank Select addresses(BA0, BA1) are required. The Bank Activation command
must be applied before any Read or Write operation is executed. The delay from the Bank Activation command to the first read or
write command must meet or exceed the minimum of RAS to CAS delay time(tRCD min). Once a bank has been activated, it must be
precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between inter-
leaved Bank Activation commands(Bank A to Bank B and vice versa) is the Bank to Bank delay time(tRRD min).
Bank Activation Command Cycle
012
CK
CK
3
Bank A
Address Row Addr.
Command
Bank A
Activate
RAS-CAS delay(tRCD)
NOP
NOP
NOP
45
Tn
Tn+1
Tn+2
Bank A
Col. Addr.
Write A
with Auto
Precharge
NOP
Bank B
Row Addr.
Bank A
Row. Addr.
RAS-RAS delay time(tRRD)
Bank B
Activate
NOP
Bank A
Activate
ROW Cycle Time(tRC)
: Dont care
Figure.4 Bank activation command cycle timing
Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating
RAS, CS, CAS, and deasserting WE at the same clock sampling(rising) edge as described in the command truth table. The length of
the burst and the CAS latency time will be determined by the values programmed during the MRS cycle.
Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating
RAS, CS, CAS, and WE at the same clock sampling(rising) edge as described in the command truth table. The length of the burst will
be determined by the values programmed during the MRS cycle.
11 March 2004

11 Page







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