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PDF K4S643232F-TC70 Data sheet ( Hoja de datos )

Número de pieza K4S643232F-TC70
Descripción 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! K4S643232F-TC70 Hoja de datos, Descripción, Manual

K4S643232F
CMOS SDRAM
2M x 32 SDRAM
512K x 32bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 1.0
January 2002
Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 (Jan. 2002)
-1-

1 page




K4S643232F-TC70 pdf
K4S643232F
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
System clock
CS Chip select
CKE
Clock enable
A0 ~ A10
Address
BA0,1
Bank select address
RAS
Row address strobe
CAS
Column address strobe
WE Write enable
DQM0 ~ 3 Data input/output mask
DQ0 ~ 31
VDD/VSS
Data input/output
Power supply/ground
VDDQ/VSSQ Data output power/ground
NC No Connection
CMOS SDRAM
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No connection on the device.
Rev. 1.0 (Jan. 2002)
-5-

5 Page





K4S643232F-TC70 arduino
K4S643232F
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address BA0 ~ BA1
Function RFU
A10/AP
RFU
A9
W.B.L
A8 A7
TM
A6 A5 A4
CAS Latency
CMOS SDRAM
A3 A2 A1 A0
BT Burst Length
Test Mode
CAS Latency
Burst Type
Burst Length
A8 A7
Type
A6 A5 A4 Latency A3
Type
A2 A1 A0 BT = 0 BT = 1
0
0 Mode Register Set
00
0 Reserved 0 Sequential 0 0 0
1
1
01
Reserved
0 0 1 Reserved 1 Interleave 0 0 1
2
2
10
Reserved
010
2
01 0
4
4
11
Reserved
011
3
01 1
8
8
Write Burst Length
1 0 0 Reserved
1 0 0 Reserved Reserved
A9 Length
0 Burst
1 0 1 Reserved
1 1 0 Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 Single Bit
1 1 1 Reserved
1 1 1 Full Page Reserved
Full Page Length : x32 (256)
POWER UP SEQUENCE
SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
2. RFU (Reserved for future use) should stay "0" during MRS cycle.
Rev. 1.0 (Jan. 2002)
- 11

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