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PDF K4S511632M Data sheet ( Hoja de datos )

Número de pieza K4S511632M
Descripción 512Mbit SDRAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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K4S511632M
CMOS SDRAM
512Mbit SDRAM
8M x 16bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 0.3
May. 2002
Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.3 May. 2002

1 page




K4S511632M pdf
K4S511632M
CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
IOS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Unit
V
V
°C
W
mA
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
VDD, VDDQ
VIH
VIL
VOH
VOL
ILI
Min
3.0
2.0
-0.3
2.4
-
-10
Typ Max
3.3 3.6
3.0 VDD+0.3
0 0.8
--
- 0.4
- 10
Unit
V
V
V
V
V
uA
Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns.
3. Any input 0V VIN VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Note
1
2
IOH = -2mA
IOL = 2mA
3
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Pin
Clock
RAS, CAS, WE, CS, CKE
DQM
Address
DQ0 ~ DQ15
Symbol
CCLK
CIN
CDQM
CADD
COUT
Min
2.5
2.5
2.5
2.5
4.0
Notes : 1. -75 only specify a maximum value of 3.5pF
2. -75 only specify a maximum value of 3.8pF
3. -75 only specify a maximum value of 6.0pF
Max
4.0
5.0
5.0
5.0
6.5
Unit
pF
pF
pF
pF
pF
Rev. 0.3 May. 2002

5 Page





K4S511632M arduino
K4S511632M
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
Command
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP
A11, A12,
A9 ~ A0
Note
Register
Mode register set
H X LL L L X
OP code
1,2
Auto refresh
H
3
H
LL
LHX
X
Entry
L
3
Refresh
Self
refresh
Exit
LH HH
LH
X
X
3
HX
XX
3
Bank active & row addr.
H X L L H H X V Row address
Read &
Auto precharge disable
column address Auto precharge enable
H
X LH L H X V
L
Column
4
address
(A0~A9)
H 4,5
Write &
Auto precharge disable
column address Auto precharge enable
H
X LH L L X V
L
Column
4
address
(A0~A9)
H 4,5
Burst stop
H X LH H L X X 6
Precharge
Bank selection
All banks
VL
H X LL HL X
XH
X
Clock suspend or
active power down
Entry
Exit
HX
XX
HL
X
LV
VV
L H XX X X X
X
Precharge power down mode
Entry
Exit
HX
XX
HL
X
LH HH
HX
XX
LH
X
LV
VV
X
DQM
H X VX7
No operation command
HX
XX
HX
X
LH HH
X
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes : 1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.3 May. 2002

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