|
|
PDF S6B0796 Data sheet ( Hoja de datos )
| Número de pieza | S6B0796 | |
| Descripción | 240 SEG / COM DRIVER FOR STN LCD | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de S6B0796 (archivo pdf) en la parte inferior de esta página. Total 32 Páginas | ||
|
No Preview Available !
S6B0796
240 SEG / COM DRIVER FOR STN LCD
January, 2000
Ver. 1.0
Prepared by: Gyeong-Nam, Kim
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
1 page  
S6B0796 PRELIMINARY SPEC. VER. 1.0
BLOCK DIAGRAM
240 SEG / COM DRIVER FOR STN LCD
FR 260
DISPOFFB 257
EIO1 259
EIO2 247
LP 258
XCK 256
VOR V12R V43R V5L
268 267 266 265
Y1 Y2
12
Y239 Y 240
239 240
LEVEL
SHIFTER
ACTIVE
CONTROL
CONTROL
LOGIC
240 BITS 4-LEVEL DRIVER
240
240 BITS LEVEL SHIFTER
240
240 BITS LINE LATCH/SHIFTER
REGISTER
16 16 16 16 16
16 16 16
8BITS*2
DATA
LATCH
244 V5L
243 V43L
242 V12L
241 VOL
L/R 261
MD 262
S/C 246
8
SP CONVERSION & DATA CONTROL
(4 to 8 or 8to 8)
DATA LATCH CONTROL
248 249 250 251 252 253 254 255
D I0 D I1 D I2 D I3 DI4 DI5 DI6 DI7
245 264
VDD VSS
Figure 1. Block Diagram
5
5 Page 
S6B0796 PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
PIN FUNCTION
Segment mode
Symbol
Function
VDD Logic system power supply pin connects to +2.4 to +5.5V
VSS Ground pin connects to 0 V
V0R, V0L
V12R , V12L
V43R , V43L
V5R , V5L
Power supply pin for LC driver voltage bias.
. Normally, the bias voltage used is set by a resistor divider.
. Ensure that voltage are set such that VSS ≤ V5 < V43 < V12 < V0.
. To further reduce the difference between the output waveforms of LC driver
output pins Y1 and Y160, externally connect ViR and ViL (I = 0, 12, 43, 5)
Input pin for display data
. In 4-bit parallel input mode, input data into the 4 pins DI0 – DI3.
DI0 – DI7
Connect DI4 – DI7 to VSS or VDD.
. In 8-bit parallel input mode, input data into the 8 pins DI0 – DI7.
XCK
Clock input pin for taking display data
. Data is read on the falling edge of the clock pulse.
Latch pulse input pin for display data
LP
. Data is latched on the falling edge of the clock pulse.
Direction selection pin for reading display data
L/R . When set to VSS level “L”, data is read sequentially from Y240 to Y1.
. When set to VDD level H”, data is read sequentially from Y1 to Y240.
Control input pin for output deselect level
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
DISPOFFB
. When set to VSS level “L”, the LC drive output pins (Y1 - Y240) are set to level
V5.
. While set to “L”, the contents of the line latch are reset, but read the display
data in the data latch regardless of condition of DISPOFFB.
When the DISPOFFB function is canceled, the driver outputs deselect level
(V12 or V43), then outputs the contents of the data latch on the next.
Falling edge of the LP. That time, if DISPOFFB removal time can not keep regulation what is
shown AC characteristics (page 21), can not output the reading data correctly.
11
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet S6B0796.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| S6B0794 | 160 SEG / COM DRIVER FOR STN LCD | Samsung semiconductor |
| S6B0796 | 240 SEG / COM DRIVER FOR STN LCD | Samsung semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |