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PDF S5L9286 Data sheet ( Hoja de datos )

Número de pieza S5L9286
Descripción DIGITAL SIGNAL PROCESSOR FOR CDP
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! S5L9286 Hoja de datos, Descripción, Manual

DIGITAL SIGNAL PROCESSOR FOR CDP
DIGITAL SIGNAL PROCESSOR
The S5L9826F01 is a CMOS integrated circuit designed for the Digital
Audio Signal Processor for Compact Disc Player. It is a monolithic IC that
builts-in 16-bit Digital Analog Convertor, ESP Interface and Digital De-
emphasis additional conventional DSP function.
80-QFP-1420C
FEATURES
• EFM data demodulation
• Frame sync detection / protection / insertion
• Powerful error correction (C1: 2 error; C2: 4 erasure)
• Interpolation
• 8fs digital filter (51th+13th+9th)
• Subcode data serial output
• CLV servo controller
• MICOM interface
• Digital audio output
• Digital de-emphasis
• ESP interface
• Built-in 16K SRAM
• Built-in digital PLL
• Double speed play available
• Built-in 16-bit D/A converter
• VDD = 5V
ORDERING INFORMATION
Device
S5L9286F01-Q0R0
Package
80-QFP-1420C
Tempe. Range
-20oC – +75oC
S5L986F01
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S5L9286 pdf
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L986F01
PIN DESCRIPTION (continued)
PIN NO
30
31
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49
50
51
52
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SYMBOL
SQDT
SQOK
SBCK
SDAT
DVDD1
MUTE
MLT
MDAT
MCK
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
/PBCK
DVSS2
FSDW
ULKFS
/JIT
C4M
C16M
/WE
/CS
IO DESCRIPTION
O Serial output of Subcode-Q data
O The CRC (Cycle Redundancy Check) check result signal output of Subcode-Q
I Clock for output subcode data
O Subcode serial data output
- Digital VDD1
I Mute control input ("H": Mute ON)
I Latch Signal Input from Micom (Schmit Trigger)
I Serial data input from Micom (Schmit Trigger)
I Serial clock input from Micom (Schmit Trigger)
I/O SRAM data I/O port 8 (MSB)
I/O SRAM data I/O port 7
I/O SRAM data I/O port 6
I/O SRAM data I/O port 5
I/O SRAM data I/O port 4
I/O SRAM data I/O port 3
I/O SRAM data I/O port 2
I/O SRAM data I/O port 1 (LSB)
I/O Monitoring output for error correction (RA0)
I/O Monitoring output for error correction (RA1)
I/O Monitoring output for error correction (RA2)
I/O Monitoring output for error correction (RA3)
I/O Monitoring output for error correction (RA4)
I/O Output of VCO/2 (4.3218MHz) (RA5)
I/O Digital ground 2
I/O Window or unprotected frame sync (RA6)
I/O Frame sync protection state (RA7)
I/O Display of either RAM overflow or underflow for + 4 frame jitter margin (RA8)
I/O Only monitoring signal (4.2336MHz) (RA9)
I/O 16.9344MHz signal output(RA10)
I/O Terminal for test
I/O Terminal for test
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S5L9286 arduino
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L986F01
CONTROL REGISTER DESCRIPTION
• CNTL-Z
This register carries out the following functions: audios zero cross mute, phase pin control,
phase servos control signal management, and the decision whether or not to include SQOK data
in SQDT.
Bit 3 2 1 0
Identifier
ZCMT
-
NCLV
CRCQ
ZCMT
Zero cross mute
0 Zero cross mute is OFF
1 Zero cross mute is ON
NCLV
Phase servos control
0 Phase Servo operated by frame sync
1 Phase Servo controlled by base counter
CRCQ
Decide whether or not to include SQOK data in SQDT
0 SQDT output not including SQOK
1 SQDT = SQOK, when SOS1 is “H”.
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