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PDF S5L9250B01-Q0R0 Data sheet ( Hoja de datos )

Número de pieza S5L9250B01-Q0R0
Descripción The CD-ROM 48X 1 chip receives the input signal read from the CD-DA/VIDEO-CD/CD-ROM disc after handling by the RF amplifier.
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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DATA SHEET
S5L9250B
INTRODUCTION
The CD-ROM 48X 1 chip receives the input signal read from the CD-DA/VIDEO-CD/CD-ROM disc after handling
by the RF amplifier. The signal is input into the digital servo block which has a built-in DSP core, and goes
through focus and tracking adjustments. The RF signal input into a data path goes through the data slicer, PLL,
EFM demodulator, C1/C2 ECC and the audio handling block. In the case of a CD-DA, the signal is output through
the 1-bit DAC. In the case of a CD-ROM, the signal is input into an external CD-ROM controller for handling, then
transmitted to the host through the ATAPI I/F. Also, if you operate the CD-DA in audio buffering mode while
already in CAV mode, the signal is stored in the CD-ROM controller DRAM at high speed, then output at 1x from
the CD-ROM controller, after passing through the 1-bit DAC built-in to the S5L9250B.
FEATURES
Main Features
Digital servo, CD-DSP, 1-bit DAC.
33.8688MHz crystal.
Supports CLV 4X and 8X.
Supports CAV MAX 16X, 20X, 24X, 32X, 40X, and 48X.
Interrupt (SINTB)
MICOM interface
Digital Servo Block
Automatic adjusting feature (focus/tracking loop offset, balance, loop gain)
Built-in AGC feature that adapts to work optimally with various disc types
Built-in search algorithm for speed control
Servo monitor signal generation (FOK, MIRROR, TZC, ANTI-SHOCK)
Various loop filter coefficient selection by MICOM
Built-in algorithm for handling defects/shocks
Disc discriminating data out (FEpk, SBADpk)
RF IC and serial interface
Built-in 10-bit DAC (Focus/Tracking/SLD)
OAK DSP core
CD Digital Signal Processing Block
Wide capture range analog PLL
Data Slicer using duty feedback method
EFM demodulation
Sync detection, protection, insertion
CLV, CAV disc spindle motor control
C1/C2 ECC
Built-in 16 K SRAM for ECC
Subcode P - W handling feature
CD-DA Audio handling feature
SUB-Q De-interleaving & CRC check
High speed data transmission support by CD-ROM decoder block for audio buffering (sync mode
selection
between subcode sync and CD-DA data)
Digital audio out block
Subcode sync. Insertion, Protection
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S5L9250B01-Q0R0 pdf
DATA SHEET
S5L9250B
PIN DESCRIPTION
Table 1. Pin Description
No Name
Description
Related I/O
Block
1 VSSA1 Analog ground (EQ controller)
-P
2 VREFI VREF input
SERVO I
3 VSSA2 Analog ground (for servo ADC use)
-P
4 RFRP RF envelope signal
SERVO I
5 RFCT RF envelope's center detection signal SERVO I
6 SBAD FOK, DFCT generating SUB-BEAM ADD SERVO I
signal (E+F)
7 CEI ERROR signal for center servo use SERVO I
8 TZCA TZC signal generating signal (=TE)
SERVO I
9 TE Tracking error signal
SERVO I
10 TELPF TE defect holding pin
SERVO I
11 FE Focusing error signal
SERVO I
12 FELPF FE defect holding pin
SERVO I
13 VCCA2 Analog 3.3V power (for servo ADC use)
-
P
14 AOUT Analog out
SERVO O
15 PPUMP Pump out for PLL use (filter)
SERVO O
16 VSSA3 Analog ground (for servo DAC use)
-P
17
TRD
Tracking drive signal (10-bit DAC)
SERVO O
18
FOD
Focusing drive signal (10-bit DAC)
SERVO O
19 SLED0 Stepping control signal 0/DC motor
control signal
SERVO O
20 SLED1 Stepping control signal 1
SERVO O
21 SPINDLE Spindle controlling PWM output
CLV O
22 VREFO VREF out for driver IC
SERVO O
23 VCCA3 Analog 3.3V power (for DAC use)
-P
24 SMON Spindle motor on/off
CLV O
25 DVSS1 Digital GND
(for output PAD + PRE driver)
-P
26 GPIO0 General purpose I/O 0
B
27 STOP/GPIO LIMIT switch/sled position sensor
PS0/general purpose I/O
SERVO B
28 PS1/GPIO Sled position sensor signal 1/general
purpose I/O
SERVO B
29 FG Frequency generator signal (for CAV) CLV I
Pad Type
VSSA
PICA
VSSA
PICA
PICA
PICA
PICA
PICA
PICA
PICA
PICA
PICA
VCCA
POBA
POBA
VSSA
POBA
POBA
POBA
POBA
POBA
POBA
VCCA
PHOB4
VSSOP
PHBCT4
PHBCT4
PHBCT4
PHIC
To/From
-
RF
-
RF
RF
RF
RF
RF
RF
-
RF
-
-
MONI
-
-
DRV
DRV
DRV
DRV
-
SLED
-
MOTOR
-
-
-
MOTOR
5

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S5L9250B01-Q0R0 arduino
DATA SHEET
RECOMMENDED OPERATING CONDITIONS
No Item
1 Operating temperature
2 DC supply voltage
3.3V
5.0V
Symbol
Topr
VDD3
VDD5
Spec.
0 - 70
3.0 - 3.6
4.75 5.25
S5L9250B
Unit
°C
V
V
DC CHARACTERISTICS: (VDD = 5V, VSS= 0V, Ta = 25°C)
ITEM
'H' input voltage1
'L' input voltage1
'H' input voltage2
'L' input voltage2
'H' input current1
'L' input current1
'H' input current2
'L' input current2
'H' output voltage1
'L' output voltage1
Tri-state output leakage current
Quiescent supply current
Symbol
VIH(1)
VIL(1)
VIH(2)
VIL(2)
IIH(1)
IIL(1)
IIH(2)
IIL(2)
VOH(1)
VOL(1)
IOZ
IDS
Test Condition
MIN
3.5
-
2.0
Vin = VDD
-10
Vin = VSS
-10
Vin = VDD
10
Vin = VSS
-200
IOH = -2/-4/-8mA
IOL = 2/4/8mA
Vout = VSS or VDD
2.4
-
-10
Vin = VSS
NOTES:
1. Related pins: All CMOS interface input terminals (PHIC)
All tri-state bi-directional pad's input terminals (PHBCT4)
2. Related pins: All CMOS schmitt trigger input terminals (PHIS, PHISU)
3. Related pins: All input terminals, bi-directional pad's input mode terminals.
4. Related pins: All input buffers with pull-down.
5. Related pins: All input buffers with pull-up.
6. Related pins: All output terminals.
7. Related pins: Tri-state output buffer (PHBCT4)
TYP
-
-
-
-
100
-100
-
-
-
MAX
-
1.5
0.8-
10
10
200
-10
-
0.4
10
100
Unit
V
V
V
V
uA
uA
uA
uA
V
V
uA
uA
Note
(1)
(1)
(2)
(2)
(3)
(3)
(4)
(5)
(6)
(6)
(7)
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