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PDF S5D2650 Data sheet ( Hoja de datos )
| Número de pieza | S5D2650 | |
| Descripción | MULTISTANDARD VIDEO DECODER/SCALER | |
| Fabricantes | Samsung semiconductor | |
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S5D2650 Data Sheet
MULTISTANDARD VIDEO DECODER/SCALER
The S5D2650 converts analog NTSC, PAL or SECAM
video in composite, S-video, or component format to
digitized component video. Output data can be selected for
CCIR 601 or square pixel sample rates in either YCbCr or
RGB formats. The digital video can be scaled down in both
the horizontal and vertical directions. The S5D2650 also
decodes Intercast, Teletext, Closed Caption, and SMPTE
data with a built-in bit data slicer. Digitized CVBS data can
be output directly during VBI for external processing.
MULTIMEDIA VIDEO
100 PQFP
FEATURES
• Accepts NTSC-M/N/4.43, PAL-M/N/B/G/H/I/D/K/L and
SECAM formats with auto detection
• 6 analog inputs: 2 S-video, 4 composite, or 2 3-wire
YPbPr component video
• YPbPr Progressive input support(720x480p)
• 3-line luma and chroma comb filters including
adaptive luma comb for NTSC
• Programmable luma bandwidth,
brightness, and edge enhancement
contrast,
• Programmable chroma bandwidth, hue, and
saturation
• High quality horizontal and vertical down scaler
• Intercast, Teletext and Closed Caption decoding with
built-in bit slicer
• Direct output of digitized CVBS during VBI for
Intercast application
• Analog square pixel or CCIR 601 sample rates
• Output in 4:4:4, 4:2:2, or 4:1:1 YCbCr component, or
24-bit or 16-bit RGB formats with dithering
• YCbCr 4:2:2 output can be 8 or 16 bits wide with
embedded timing reference code support for 8-bit
mode
• Simultaneous scaled and non-scaled digital output
ports outputs for 8-bit mode.
• Direct access to scaler via bi-directional digital port.
• Programmable Gamma correction table
• Programmable timing signals
• Industry standard IIC interface
ORDERING INFORMATION
Device Package Temperature Range
S5D2650 100 PQFP
0°~+70°C
APPLICATIONS
• Multimedia
• Digital Video
• Video Capture/Editing
• LCD-TV
• Surveillance system
RELATED PRODUCTS
• KS0123 MULTISTANDARD VIDEO ENCODER
• KS0125 MULTISTANDARD VIDEO ENCODER
• KS0127B VIDEO DECODER
ELECTRONICS
PAGE 1 OF 95
7/18/03
1 page  
S5D2650 Data Sheet
MULTIMEDIA VIDEO
PIN DESCRIPTION (Continued)
Pin Name
PID
OEN
Pin #
17
15
CK 18
CK2
CCDAT
21
73
CCEN
74
MULTI-PURPOSE I/O PORTS
PORTA
58
PORTB(SCH) 24
Type
Description
O PAL ID flag. Pahse Alternate Line flag
I Output data, timing and clock 3-state output control.
(Default : tied to VDD)
I/O System clock. (Default : 27MHz output. When the EXV port is used
as an input, this can be programmed as an input system clock.)
O Pixel rate output clock (Default : 13.5 MHz)
O Sliced VBI data output. Data can be from Closed Caption, Teletext,
Intercast, or WSS type encoded data.
O When high, this pin indicates that valid VBI data is being clocked out
at the CCDAT pin or at the digital video output.
I/O Multi-purpose I/O portA.
I/O Multi-purpose I/O portB.
HOST INTERFACE
SCLK
75
SDAT
72
AEX0 - AEX1 69 - 70
I Serial clock for IIC host interface. (5V tolerant schmitt trigger pin)
I/O Serial data for IIC host interface.(5V tolerant schmitt triggered open
drain Pins)
I Device ID selection for IIC host interface.
POWER AND GROUND
VDD3
9,20,59
3.3V Digital power supply for input, output buffers.
VDD1
11,12,42,43,66, 1.8V Digital power supply for core logic.
67
VDDA
85,89,93
3.3V Analog power supply for ADC, AGC and reference circuits.
VDDP
98
3.3V Analog power supply for clock generation circuit(PLL).
VSS
1,2,6,13,14,19,
40,41,49-52,60,
64,65,77-80,
81-83,87,91,95,
96
GND Common ground.
VSSP
100
GND Common ground for PLL.
ELECTRONICS
PAGE 5 OF 95
7/18/03
5 Page 
S5D2650 Data Sheet
MULTIMEDIA VIDEO
When in digital input mode, all programmable timing registers (such as HAVB,HAVE, HS2B etc.) are still functional.
If HS1 and VS are programmed as inputs, the associated output timing controls such as HS1B,E will have no
effect. An example of horizontal timing for digital input is shown in Figure 4.
HS1
Programmable, when an
output - Any input phase
is acceptable
This HS1 location can also come
From a 656 SAV code
Constant to internal counter reference
EXV[7:0]
80 10 80 10 80 10 U0 Y0 V0 Y1 U2 Y2 V2 Y3 U4 Y4 V4 Y5 U6 Y6 V6 Y7 Ux Yx Vx Yx Ux Yx Vx Yx Vx
Data group delay through chip --
Y[7:0]
Y output for OFMT=2 is
shown, any 8 or 16 bit
output format is allowed.
80 10 80 10 80 10 U0 Y0 V0 Y1 U2 Y2 V2 Y3 U4 Y4 V4 Y5 U6 Y6 V6 Y7 Ux Yx Vx Yx Ux
Fully programmable HAVB location
based on internal counter
HAV -- fully programmable,
Defines location of first, last pixel
and defines Cb,Y,Cr data location
Fully programmable
HAVE location
HAV
CK
CK2
CK can be input or output
The CK2 output clock phasing
is aligned to the HAV leading
edge
Figure 4. Horizontal Timing for EXV Port as Digital Input
1.1.5. Additional Information for Analog Component Video Input
For the S5D2650 to correctly set the V component phase in PAL mode analog component video input mode,
PORTA (pin 58) need to be connected VSS. PORTA has to be configured as input (DIRA = 0) and connected to the
internal CBG signal (DATAA[2:0] = 3). Also S5D2650 supports progressive analog component input.
The following registers are required for analog component video input:
INSEL[2:0] = 6,7 PROG = 0(interlace), 1(progressive).
DATAA[2:0] = 3. CKILL[1:0] = 2. CDMLPF = 1.
SAT[7:0] = 79.
MNYCMB = 1. YCMBCO[2:0] = 4.
TSTCGN = 1. UOFFST[5:4] = VOFFST[5:4] = 3.
UOFFST[3:0] = C. VOFFST[3:0] = 2. VGAIN[7:0] = 1D. DMCTL[1:0] = 2 or 3
ELECTRONICS
PAGE 11 OF 95
7/18/03
11 Page | ||
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| PDF Descargar | [ Datasheet S5D2650.PDF ] | |
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