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PDF S524L50X51 Data sheet ( Hoja de datos )

Número de pieza S524L50X51
Descripción 16K-bit Serial EEPROM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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S524L50X51
16K-bit
Serial EEPROM
Data Sheet
OVERVIEW
The S524L50X51 serial EEPROM has a 16 Kbits (2,048 bytes) capacity, supporting the standard I2C™-bus serial
interface. It is fabricated using Samsung’s most advanced CMOS technology. One of its major features is a
hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled
by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 16 bytes of data into
the EEPROM in a single write operation. Another significant feature of the S524L50X51 is its support for fast
mode and standard mode.
FEATURES
I2C-Bus Interface
Two-wire serial interface
Automatic word address increment
EEPROM
16 Kbits (2,048 bytes) storage area
16-byte page buffer
Typical 3 ms write cycle time with
auto-erase function
Hardware-based write protection for the entire
EEPROM (using the WP pin)
EEPROM programming voltage generated
on chip
1,000,000 erase/write cycles
100 years data retention
Operating Characteristics
Operating voltage: 2.0 V to 5.5 V
Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200 µA at 5.5 V
— Maximum stand-by current: < 2 µA at 2.0 V
Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 400 V (MM)
Packages
8-pin DIP, SOP, and TSSOP
5-1

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S524L50X51 pdf
DATA SHEET
S524L50X51 SERIAL EEPROM
FUNCTION DESCRIPTION
I2C-BUS INTERFACE
The S524L50X51 supports the I2C-bus serial interface data transmission protocol. The two-wire bus consists of a
serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a
pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as a “transmitter” and any device that gets data from the bus is
a “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions,
controlling bus access. Only one S524L50X51 devices can be connected to the I2C-bus as slaves (see Figure 5-
6). Both the master and slaves can operate as a transmitter or a receiver, but the master device determines
which bus operating mode would be active.
SDA
SCL
Master
Bus Master
(Transmitter/
Receiver)
Slave
S524L50X51
Figure 5-6. Typical Configuration
VCC VCC
RR
5-5

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S524L50X51 arduino
DATA SHEET
S524L50X51 SERIAL EEPROM
HARDWARE-BASED WRITE PROTECTION
You can also write-protect the entire memory area of the S524L50X51. This method of write protection is
controlled by the state of the Write Protect (WP) pin.
When the WP pin is connected to VCC, any attempt to write a value to the memory is ignored.
The S524L50X51 will acknowledge slave and word address, but it will not generate an acknowledge after
receiving first byte of data. In this situation the write cycle will not be started when a stop condition is generated.
By connecting the WP pin to VSS, the write function is allowed for the entire memory.
These write protection features effectively change the EEPROM to a ROM in order to protect data from being
overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on
the bus, but data bytes are not acknowledged.
The WP pin is internally pulled down to VSS.
CURRENT ADDRESS BYTE READ OPERATION
The internal word address pointer maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access
data at address “n+1”.
When the S524L50X51 receives a slave address with the R/W bit set to “1”, it issues an ACK and sends eight bits
of data. In a current address byte read operation the master does not acknowledge the data, and it generates a
Stop condition, forcing the S524L50X51 to stop the transmission (see Figure 5-12).
Start Slave Address
Data
Stop
AN
CO
K
A
C
K
Figure 5-12. Current Address Byte Read Operation
5-11

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