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PDF S524C80D41 Data sheet ( Hoja de datos )

Número de pieza S524C80D41
Descripción 1K/2K/4K/8K-bit Serial EEPROM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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S524C20D11/20D21/80D41/80D81
1K/2K/4K/8K-bit
Serial EEPROM
Data Sheet
OVERVIEW
The S524C20D11/20D21/80D41/80D81 serial EEPROM has a 1,024/2,048/4,096/8,192-bit (128/256/512/1,024-
byte) capacity, supporting the standard I2C™-bus serial interface. It is fabricated using Samsungs’ most
advanced CMOS technology. One of its major feature is a hardware-based write protection circuit for the entire
memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-
page write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another
significant feature of the S524C20D11/20D21/80D41/80D81 is its support for fast mode and standard mode.
FEATURES
I2C-Bus Interface
Two-wire serial interface
Automatic word address increment
EEPROM
1K/2K/4K/8K-bit (128/256/512/1,024-byte)
storage area
16-byte page buffer
Typical 3.5 ms write cycle time with
auto-erase function
Hardware-based write protection for the entire
EEPROM (using the WP pin)
EEPROM programming voltage generated
on chip
1,000,000 erase/write cycles
100 years data retention
Operating Characteristics
Operating voltage
— 2.5 V to 5.5 V (write)
— 2.2 V to 5.5 V (read)
Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200 µA at 5.5 V
— Maximum stand-by current: < 5 µA at 3.3 V
Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
Electrostatic discharge (ESD)
— 3,000 V (HBM)
— 300 V (MM)
Packages
8-pin DIP, SOP, and TSSOP
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S524C80D41 pdf
DATA SHEET
S524C20D11/20D21/80D41/80D81 SERIAL EEPROM
FUNCTION DESCRIPTION
I2C-BUS INTERFACE
The S524C20D11/20D21/80D41/80D81 supports the I2C-bus serial interface data transmission protocol. The two-
wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be
connected to VCC by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus
is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop
conditions, controlling bus access. Using the A0,A1 and A2 input pins, up to eight S524C20D11/20D21 (four
S524C80D41, two for S524C80D81) devices can be connected to the same I2C-bus as slaves (see Figure 3-6).
Both the master and slaves can operate as transmitter or receiver, but the master device determines which bus
operating mode would be active.
VCC VCC
RR
SDA
SCL
Bus Master
(Transmitter/
Receiver)
MCU
Slave 1
S524C20D21
Tx/Rx
A0 A1 A2
Slave 2
S524C20D21
Tx/Rx
A0 A1 A2
Slave 3
S524C20D21
Tx/Rx
A0 A1 A2
To VCC or VSS
To VCC or VSS
To VCC or VSS
NOTES:
1. The A0 does not affect the device address of the S524C80D41.
2. The A0, A1 do not affect the device address of the S524C80D81.
Slave 8
S524C20D21
Tx/Rx
A0 A1 A2
To VCC or VSS
Figure 3-6. Typical Configuration (16 Kbits of Memory on the I2C-Bus)
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S524C80D41 arduino
DATA SHEET
S524C20D11/20D21/80D41/80D81 SERIAL EEPROM
HARDWARE-BASED WRITE PROTECTION
You can also write-protect the entire memory area of the S524C20D11/20D21/80D41/80D81. This method of
write protection is controlled by the state of the Write Protect (WP) pin.
When the WP pin is connected to VCC, any attempt to write a value to the memory is ignored.
The S524C20D11/20D21/80D41/80D81 will acknowledge slave and word address, but it will not generate an
acknowledge after receiving the first byte of the data. Thus the write cycle will not be started when the stop
condition is generated. By connecting the WP pin to VSS, the write function is allowed for the entire memory.
These write protection features effectively change the EEPROM to a ROM in order to prevent data from being
overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on
the bus, but data bytes are not acknowledged.
CURRENT ADDRESS BYTE READ OPERATION
The internal word address pointer maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access
data at address “n+1”.
When the S524C20D11/20D21/80D41/80D81 receives a slave address with the R/W bit set to “1”, it issues an
ACK and sends the eight bits of data. The master does not acknowledge the transfer but it does generate a Stop
condition. In this way, the S524C20D11/20D21/80D41/80D81 effectively stops the transmission (see Figure 3-
12).
Start Slave Address
Data
Stop
AN
CO
K
A
C
K
Figure 3-12. Current Address Byte Read Operation
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