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PDF S524C20D20 Data sheet ( Hoja de datos )

Número de pieza S524C20D20
Descripción 1K/2K/4K/8K-bit Serial EEPROM with software write protect
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! S524C20D20 Hoja de datos, Descripción, Manual

S524C20D10/20D20/80D40/80D80
1K/2K/4K/8K-bit
Serial EEPROM
with software write protect
Data Sheet
OVERVIEW
The S524C20D10/20D20/80D40/80D80 serial EEPROM has a 1,024/2,048/4,096/8,192-bit (128/256/512/1,024-
byte) capacity, supporting the standard I2C™-bus serial interface. It is fabricated using Samsungs’ most
advanced CMOS technology. Important features are a hardware-based write protection circuit for the entire
memory area and software-based write protection logic for the lower 128 bytes. Hardware-based write protection
is controlled by the state of the write-protect (WP) pin. The software-based method is one-time programmable
and permanent. Using one-page write mode, you can load up to 16 bytes of data into the EEPROM in a single
write operation. Another significant feature of the S524C20D10/20D20/80D40/80D80 is its support for fast mode
and standard mode.
FEATURES
I2C-Bus Interface
Two-wire serial interface
Automatic word address increment
EEPROM
1K/2K/4K/8K-bit (128/256/512/1,024-byte)
storage area
16-byte page buffer
Typical 3.5 ms write cycle time with
auto-erase function
Hardware-based write protection for the entire
EEPROM (using the WP pin)
Software-based write protection for the lower
128-byte EEPROM
EEPROM programming voltage generated
on chip
1,000,000 erase/write cycles
100 years data retention
Operating Characteristics
Operating voltage
— 2.5 V to 5.5 V (write)
— 2.2 V to 5.5 V (read)
Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200 µA at 5.5 V
— Maximum stand-by current: < 5 µA at 3.3 V
Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
Electrostatic discharge (ESD)
— 3,000 V (HBM)
— 300 V (MM)
Packages
8-pin DIP, SOP, and TSSOP
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S524C20D20 pdf
DATA SHEET
S524C20D10/20D20/80D40/80D80 SERIAL EEPROM
FUNCTION DESCRIPTION
I2C-BUS INTERFACE
The S524C20D10/20D20/80D40/80D80 supports the I2C-bus serial interface data transmission protocol. The two-
wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be
connected to VCC by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus
is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop
conditions, controlling bus access. Using the A0,A1 and A2 input pins, up to eight S524C20D10/20D20 (four for
S524C80D40, two for S524C80D80) devices can be connected to the same I2C-bus as slaves (see Figure 4-6).
Both the master and slaves can operate as transmitter or receiver, but the master device determines which bus
operating mode would be active.
VCC VCC
RR
SDA
SCL
Bus Master
(Transmitter/
Receiver)
MCU
Slave 1
S524C20D20
Tx/Rx
A0 A1 A2
Slave 2
S524C20D20
Tx/Rx
A0 A1 A2
Slave 3
S524C20D20
Tx/Rx
A0 A1 A2
To VCC or VSS
To VCC or VSS
To VCC or VSS
NOTES:
1. The A0 does not affect the device address of the S524C80D40.
2. The A0, A1 do not affect the device address of the S524C80D80.
Slave 8
S524C20D20
Tx/Rx
A0 A1 A2
To VCC or VSS
Figure 4-6. Typical Configuration (16 Kbits of Memory on the I2C-Bus)
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S524C20D20 arduino
DATA SHEET
S524C20D10/20D20/80D40/80D80 SERIAL EEPROM
SOFTWARE-BASED WRITE PROTECTION
You can write-protect the lower 128 bytes of the EEPROM, locations 00H–7FH, in one operation. To do this, you
simply write a value to a one-time, write-only register. Once you have applied this write protection, any write
attempt to access the lower 128-byte area is ignored. In other words, the write protection is permanent. The effect
of such a failed attempt is processed in the same way as an invalid I2C-bus protocol.
To enable write protection, you must execute a write operation to the write protection register. To access the write
protection register, you use the device address “0110”. The word address and data in this write operation can be
any value and the timing and wave form characteristics are identical to a normal byte write operation (see Figure
4-12).
Start Slave Address
Word Address
(Ignored)
Data
(Ignored)
Stop
AAA
CCC
KKK
Figure 4-12. Write Protection Operation
HARDWARE-BASED WRITE PROTECTION
You can also write-protect the entire memory area of the S524C20D10/20D20/80D40/80D80. This method of
write protection is controlled by the state of the Write Protect (WP) pin.
When the WP pin is connected to VCC, any attempt to write a value to the memory is ignored.
The S524C20D10/20D20/80D40/80D80 will acknowledge slave and word address, but it will not generate an
acknowledge after receiving the first byte of the data. Thus the write cycle will not be started when the stop
condition is generated. By connecting the WP pin to VSS, the write function is allowed for the entire memory.
These write protection features effectively change the EEPROM to a ROM in order to prevent data from being
overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on
the bus, but data bytes are not acknowledged.
4-11

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