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PDF S524AB0XB1 Data sheet ( Hoja de datos )
| Número de pieza | S524AB0XB1 | |
| Descripción | 32K/64K-bit Serial EEPROM for Low Power | |
| Fabricantes | Samsung semiconductor | |
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S524AB0X91/B0XB1
32K/64K-bit
Serial EEPROM
for Low Power
Data Sheet
OVERVIEW
The S524AB0X91/B0XB1 serial EEPROM has a 32K/64K-bit (4,096/8,192 bytes) capacity, supporting the
standard I2C™-bus serial interface. It is fabricated using Samsungs’ most advanced CMOS technology. It has
been developed for low power and low voltage applications (1.8 V to 5.5 V). One of its major feature is a
hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled
by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 32 bytes of data into
the EEPROM in a single write operation. Another significant feature of the S524AB0X91/B0XB1 is its support for
fast mode and standard mode.
FEATURES
I2C-Bus Interface
• Two-wire serial interface
• Automatic word address increment
EEPROM
• 32K/64K-bit (4,096/8,192 bytes) storage area
• 32-byte page buffer
• Typical 3 ms write cycle time with
auto-erase function
• Hardware-based write protection for the entire
EEPROM (using the WP pin)
• EEPROM programming voltage generated
on chip
• 1,000,000 erase/write cycles
• 100 years data retention
Operating Characteristics
• Operating voltage
— 1.8 V to 5.5 V
• Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 400 µA at 5.5 V
— Maximum stand-by current: < 1 µA at 5.5 V
• Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
• Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
• Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 500 V (MM)
Packages
• 8-pin DIP, SOP, and TSSOP
6-1
1 page  
DATA SHEET
S524AB0X91/B0XB1 SERIAL EEPROM
FUNCTION DESCRIPTION
I2C-BUS INTERFACE
The S524AB0X91/B0XB1 supports the I2C-bus serial interface data transmission protocol. The two-wire bus
consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected
to VCC by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as a “transmitter” and any device that gets data from the bus is
a “receiver.” The bus is controlled by a master device whic h generates the serial clock and start/stop conditions,
controlling bus access. Using the A0, A1, and A2 input pins, up to eight S524AB0X91/B0XB1 devices can be
connected to the same I2C-bus as slaves (see Figure 6-6). Both the master and slaves can operate as a
transmitter or a receiver, but the master device determines which bus operating mode would be active.
SDA
SCL
Bus Master
(Transmitter/
Receiver)
MCU
Slave 1
S524AB0X91/
B0XB1
Tx/Rx
A0 A1 A2
Slave 2
S524AB0X91/
B0XB1
Tx/Rx
A0 A1 A2
Slave 3
S524AB0X91/
B0XB1
Tx/Rx
A0 A1 A2
To VCC or VSS
To VCC or VSS
To VCC or VSS
VCC VCC
RR
Slave 8
S524AB0X91/
B0XB1
Tx/Rx
A0 A1 A2
To VCC or VSS
Figure 6-6. Typical Configuration
6-5
5 Page 
DATA SHEET
S524AB0X91/B0XB1 SERIAL EEPROM
HARDWARE-BASED WRITE PROTECTION
You can also write-protect the entire memory area of the S524AB0X91/B0XB1. This write protection is controlled
by the state of the Write Protect (WP) pin.
When the WP pin is connected to VCC, any attempt to write a value to it is ignored. The S524AB0X91/B0XB1 will
acknowledge slave and word addresses, but it will not generate an acknowledge after receiving the first byte of
data. In this situation, the write cycle will not be started when a stop condition is generated. By connecting the
WP pin to VSS, the write function is allowed for the entire memory.
These write protection features effectively change the EEPROM to a ROM in order to protect data from being
overwritten. Whenever the write function is disabled, a slave address and word addresses are acknowledged on
the bus, but data bytes are not acknowledged.
CURRENT ADDRESS BYTE READ OPERATION
The internal word address pointer maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either read or write) was to the address “n”, the next read operation would be to
access data at address “n+1”.
When the S524AB0X91/B0XB1 receives a slave address with the R/W bit set to “1”, it issues an ACK and sends
the eight bits of data. In a current address byte read operation, the master does not acknowledge the data, and it
generates a stop condition, forcing the S524AB0X91/B0XB1 to stop the transmission (see Figure 6-13).
Start Slave Address
Data
Stop
AN
CO
K
A
C
K
Figure 6-13. Current Address Byte Read Operation
6-11
11 Page | ||
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