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Descripción Dual Voltage Supervisory Circuit With Watchdog Timer
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S4242/S42WD42/S4261/S42WD61
Dual Voltage Supervisory Circuit
With Watchdog Timer(S42WD61) (S42WD42)
FEATURES
• Precision Dual Voltage Monitor
– VCC Supply Monitor
- Dual reset outputs for complex
microcontroller systems
- Integrated memory write lockout function
- No external components required
• Second Voltage Monitor Output
– Separate VLOW output
– Generates interrupt to MCU
– Generates RESET for dual supply systems
- Guaranteed output assertion to VCC - 1V
• Watchdog Timer (S42WD42, S42WD61)
– 1.6s
• Memory Internally Organized 2 x8
• Extended Programmable Functions
Available on SMS24
• High Reliability
– Endurance: 100,000 erase/write cycles
– Data retention: 100 years
OVERVIEW
The S42xxx are a precision power supervisory circuit. It
automatically monitors the device’s VCC level and will
generate a reset output on two complementary open drain
outputs. In addition to the VCC monitoring, the S42xxx also
provides a second voltage comparator input. This input
has an independent open drain output that can be wire-
OR’ed with the RESET I/O or it can be used as a system
interrupt.
The S42xxx also has an integrated 4k/16k-bit nonvolatile
memory. The memory conforms to the industry standard
two-wire serial interface. In addition to the reset circuitry,
the S42WD42/S42WD61 also has a watchdog timer.
BLOCK DIAGRAM
VCC
8
SCL 6
SDA 5
NONVOLATILE
MEMORY
ARRAY
WRITE
CONTROL
PROGRAMMABLE
RESET PULSE
GENERATOR
2 RESET#
+
VSENSE 3
1.26V
4
GND
+
VTRIP
RESET
CONTROL
PROGRAMMABLE
WATCHDOG
TIMER
(S42WD42,
S42WD61)
UV
OV
2025 T BD 2.0
7 RESET
1 VLOW#
SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 2000
2025 6.0 4/17/00
Characteristics subject to change without notice
1

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S4261S2.7S pdf
S4242/S42WD42/S4261/S42WD61
VSENSE
VULH
VLOW#
(Under-voltage detect)
tVD1
VUHL
tVD2
FIGURE 4. VSENSE UNDER-VOLTAGE FUNCTION
2025 T fig04 2.0
RESET# (in)
RESET# (out)
RESET (out)
tPURST
tPURST
FIGURE 5. RESET AS AN INPUT
2025 T fig05 2.0
2025 6.0 4/17/00
5

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S4261S2.7S arduino
S4242/S42WD42/S4261/S42WD61
Random Address Byte Read
Random address read operations allow the master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the master
issues a write command which includes the start condi-
tion and the slave address field (with the R/W bit set to
WRITE) followed by the address of the word it is to read.
This procedure sets the internal address counter of the
S42xxx to the desired address.
After the word address acknowledge is received by the
master, the master immediately reissues a start condition
followed by another slave address field with the R/W bit
set to READ. The S42xxx will respond with an acknowl-
edge and then transmit the 8-data bits stored at the
addressed location. At this point, the master does not
acknowledge the transmission but does generate the stop
condition. The S42xxx discontinues data transmission
and reverts to its standby power mode. See Figure 13 for
the address, acknowledge and data transfer sequence.
SDA Bus
Activity
** A
AA ARC
10 9 8 W K
Word Address
A
C
K
A
A AA R C
10 9 8 W K
Data Byte
101 0
0
S
T
A
Device
Type
Address
R
T
A10,A9,A8
Read/Write
0= Write
Slave Address
AAA A AA AA
765 4 32 10
101 0
1
S
T Device
A
R
Type
Address
A10,A9,A8
Read/Write
T 1= Read
Slave Address
D
7
DD
65
DD
43
DD
21
D
0
1
S
T
Lack of ACK (low)
from Master
O
P
determines last
data byte to be read
Master sends Read
request to Slave
Master Writes Word
Address to Slave
Master Requests
Data from Slave
Slave sends
Data to Master
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Shading Denotes
42xxx
SDA Output Active
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
* S4261/S42WD61 only
2025 ILL13.1
FIGURE 13. RANDOM ADDRESS BYTE READ MODE
2025 6.0 4/17/00
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