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PDF S3F380D Data sheet ( Hoja de datos )

Número de pieza S3F380D
Descripción Samsung S3C380D 16/32-bit RISC microcontroller is a cost-effective and high-performance microcontroller solution for TV applications.
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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S3C380D/F380D
PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
OVERVIEW
Samsung S3C380D 16/32-bit RISC microcontroller is a cost-effective and high-performance microcontroller
solution for TV applications.
Among the outstanding features of the S3C380D is its CPU core, a 16/32-bit RISC processor (ARM7TDMI)
designed by Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general-purpose
microprocessor macro-cell that was developed for use in application-specific and customer-specific integrated
circuits. Its simple, elegant, and fully static design is particularly suitable for cost-sensitive and power-sensitive
applications.
The S3C380D was developed using the ARM7TDMI core, CMOS standard cell, and a data path compiler. Most
of the on-chip function blocks were designed using an HDL synthesizer. The S3C380D has been fully verified in
the Samsung ASIC test environment.
By providing a complete set of common system peripherals, the S3C380D minimizes overall system costs and
eliminates the need to configure additional components.
The integrated on-chip functions that are described in this document include:
• 4-Kbyte RAM (3008-byte (1504 × 16 bits) general register and 1088-byte (544 × 16 bits) OSD/CCD RAM)
• 128-Kbyte internal program memory
• Two 14-bit PWM modules
• Three 16-bit timers
• On screen display module
• Crystal/Ceramic oscillator or external clock can be used as the clock source
• Standby mode support: SLEEP mode
• One 8-bit basic timer and 3-bit watchdog timer
• Interrupt controller (16 interrupt sources and 2 vectors)
• Five 4-bit ADCs
• Four programmable I/O ports
• 42-pin SDIP
1-1

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S3F380D pdf
S3C380D/F380D
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Pin Name
P0.0
P0.1-P0.2
P0.3
P0.4-P0.7
P1.0-P1.3
P1.4-P1.7
P2.0-P2.3
P2.4-P2.7
P3.0
PWM0
PWM1
ADC1-4
INT0-INT3
OSDHT
IRIN
CVI IN
Pin
Type
I/O
I/O
I/O
I/O
I/O
O
O
I
I
O
I
I
Table 1-1. S3C380D Pin Descriptions
Pin Description
Input mode or push-pull output mode is
software configurable.
P0.0: PWM0 (14-bit PWM Output)
General I/O Port (3-bit), Input or n-channel
open-drain output is software configurable.
Pins can withstand up to 6-volt loads. An
alternative function is supported.
P0.1: PWM1 (14-Bit PWM Output)
General I/O Port (4-bit), Input or Output
mode (push-pull or n-channel open drain) is
software configurable.
Circuit
Type
6
3
7
Input/output mode or push-pull output mode
is software configurable.
General I/O Port (4-bit), configurable for
digital input or n-channel open drain output.
P1.4-P1.7 can withstand up to 5-volt loads.
Multiplexed for alternative use as external
inputs ADC1-ADC4.
General I/O Port (4-bit), input or push-pull
output mode is software configurable.
Multiplexed for alternative use as external
interrupt inputs INT0-INT3.
6
4
2
Input mode or push-pull output mode is
software configurable. An alternative
function is supported. P2.7: OSDHT
(Halftone signal output)
Input mode or push-pull output mode is
software configurable.
Output pin for 14-bit PWM0 circuit
6
6
6
Output pin for 14-bit PWM1 circuit
3
Input for 4-bit resolution flash A/D
Converter
4
External interrupt input pins
2
Halftone control signal output for OSD
Remocon signal input
Normal mode: Remocon signal input
OTP Write mode: VPP=12.5 V
Video signal input
6
1
8
Pin
Numbers
1
Share
Pins
PWM0
2-3 PWM1
42
38-41
4-7
8-11 ADC1-
ADC4
14-17 INT0-INT3
18-21
OSDHT
35
1
2
8-11
14-17
21
36
P0.0
P0.1
P1.4-7
P2.0-3
P2.7
28 ADC0
1-5

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S3F380D arduino
S3C380D/F380D
PRODUCT OVERVIEW
CPU CORE OVERVIEW
The S3C380D CPU core is the ARM7TDMI processor, a general purpose, 32-bit microprocessor developed by
Advanced RISC Machines, Ltd. (ARM). The core's architecture is based on Reduced Instruction Set Computer
(RISC) principles. The RISC architecture makes the instruction set and its related decoding mechanisms simpler
and more efficient than with microprogrammed Complex Instruction Set Computer (CISC) systems. The resulting
benefit is high instruction throughput and impressive real-time interrupt response. Pipelining is also employed so
that all components of the processing and memory systems can operate continuously. The ARM7TDMI has a
32-bit address bus.
An important feature of the ARM7TDMI processor, differentiating it from the ARM7 processor, is a unique
architectural strategy called THUMB. The THUMB strategy is an extension of the basic ARM architecture and
consists of 36 instruction formats. These formats are based on the standard 32-bit ARM instruction set, but have
been re-coded using 16-bit wide opcodes.
Because THUMB instructions are one-half the bit width of normal ARM instructions, they produce very high-
density code. When a THUMB instruction is executed, its 16-bit opcode is decoded by the processor into its
equivalent instruction in the standard ARM instruction set. The ARM core then processes the 16-bit instruction as
it would a normal 32-bit instruction. In other words, the Thumb architecture gives 16-bit systems a way to access
the 32-bit performance of the ARM core without incurring the full overhead of 32-bit processing.
Because the ARM7TDMI core can execute both standard 32-bit ARM instructions and 16-bit Thumb instructions,
it lets you mix routines of Thumb instructions and ARM code in the same address space. In this way, you can
adjust code size and performance, routine by routine, to find the best programming solution for a specific
application.
Address Register
Address Register
Register Bank
Multiplexer
Barrel Shifter
32-Bit ALU
Write Data Register
Instruction
Decoder and
Logic Control
Instruction
Pipeline and
Read Data
Register
Figure 1-12. ARM7TDMI Core Block Diagram
1-11

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