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PDF S3C72G9 Data sheet ( Hoja de datos )

Número de pieza S3C72G9
Descripción The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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The SAM47 instruction set is specifically designed to support the large register files typically founded in most
KS57-series microcontrollers. The SAM47 instruction set includes 1-bit, 4-bit, and 8-bit instructions for data
manipulation, logical and arithmetic operations, program control, and CPU control. I/O instructions for peripheral
hardware devices are flexible and easy to use. Symbolic hardware names can be substituted as the instruction
operand in place of the actual address. Other important features of the SAM47 instruction set include:
— 1-byte referencing of long instructions (REF instruction)
— Redundant instruction reduction (string effect)
— Skip feature for ADC and SBC instructions
Instruction operands conform to the operand format defined for each instruction. Several instructions have multiple
operand formats.
Predefined values or labels can be used as instruction operands when addressing immediate data. Many of the
symbols for specific registers and flags may also be substituted as labels for operations such DA, mema, memb,
b, and so on. Using instruction labels can greatly simplify programming and debugging tasks.
       
In this section, the following SAM47 instruction set features are described in detail:
— Instruction reference area
— Instruction redundancy reduction
— Flexible bit manipulation
— ADC and SBC instruction skip condition

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S3C72G9 pdf
 
   
INSTRUCTIONS WHICH AFFECT THE CARRY FLAG
The only instructions which do not generate a skip signal, but which do affect the carry flag are as follows:
ADC
SBC
SCF
RCF
CCF
RRC
LDB
BAND
BOR
BXOR
IRET
C,(operand)
C,(operand)
C,(operand)
C,(operand)
ADC AND SBC INSTRUCTION SKIP CONDITIONS
The instructions 'ADC A,@HL' and 'SBC A,@HL' can generate a skip signal, and set or clear the carry flag, when
they are executed in combination with the instruction 'ADS A,#im'.
If an 'ADS A,#im' instruction immediately follows an 'ADC A,@HL' or 'SBC A,@HL' instruction in a program
sequence, the ADS instruction does not skip the instruction following ADS, even if it has a skip function. If,
however, an 'ADC A,@HL' or 'SBC A,@HL' instruction is immediately followed by an 'ADS A,#im' instruction, the
ADC (or SBC) skips on overflow (or if there is no borrow) to the instruction immediately following the ADS, and
program execution continues. Table 5-3 contains additional information and examples of the 'ADC A,@HL' and
'SBC A,@HL' skip feature.
Table 5-3. Skip Conditions for ADC and SBC Instructions
Sample
Instruction Sequences
ADC A,@HL
ADS A,#im
xxx
xxx
1
2
3
4
SBC A,@HL
ADS A,#im
xxx
xxx
1
2
3
4
If the result of
instruction 1 is:
Overflow
No overflow
Borrow
No borrow
Then, the execution
sequence is:
1, 3, 4
1, 2, 3, 4
Reason
ADS cannot skip
instruction 3, even if it
has a skip function.
1, 2, 3, 4
1, 3, 4
ADS cannot skip
instruction 3, even if it
has a skip function.


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S3C72G9 arduino
 
   
Name
AND
OR
XOR
COM
Table 5-12. Logic Instructions — High-Level Summary
Operand
A,#im
A,@HL
EA,RR
RRb,EA
A, #im
A, @HL
EA,RR
RRb,EA
A,#im
A,@HL
EA,RR
RRb,EA
A
Operation Description
Logical-AND A immediate data to A
Logical-AND A indirect data memory to A
Logical-AND register pair (RR) to EA
Logical-AND EA to register pair (RRb)
Logical-OR immediate data to A
Logical-OR indirect data memory contents to A
Logical-OR double register to EA
Logical-OR EA to double register
Exclusive-OR immediate data to A
Exclusive-OR indirect data memory to A
Exclusive-OR register pair (RR) to EA
Exclusive-OR register pair (RRb) to EA
Complement accumulator (A)
Bytes
2
1
2
2
2
1
2
2
2
1
2
2
2
Cycles
2
1
2
2
2
1
2
2
2
1
2
2
2
Name
ADC
ADS
SBC
SBS
DECS
INCS
Table 5-13. Arithmetic Instructions — High-Level Summary
Operand
A,@HL
EA,RR
RRb,EA
A, #im
EA,#imm
A,@HL
EA,RR
RRb,EA
A,@HL
EA,RR
RRb,EA
A,@HL
EA,RR
RRb,EA
R
RR
R
DA
@HL
RRb
Operation Description
Add indirect data memory to A with carry
Add register pair (RR) to EA with carry
Add EA to register pair (RRb) with carry
Add 4-bit immediate data to A and skip on carry
Add 8-bit immediate data to EA and skip on carry
Add indirect data memory to A and skip on carry
Add register pair (RR) contents to EA and skip on carry
Add EA to register pair (RRb) and skip on carry
Subtract indirect data memory from A with carry
Subtract register pair (RR) from EA with carry
Subtract EA from register pair (RRb) with carry
Subtract indirect data memory from A; skip on borrow
Subtract register pair (RR) from EA; skip on borrow
Subtract EA from register pair (RRb); skip on borrow
Decrement register ®; skip on borrow
Decrement register pair (RR); skip on borrow
Increment register ®; skip on carry
Increment direct data memory; skip on carry
Increment indirect data memory; skip on carry
Increment register pair (RRb); skip on carry
Bytes
1
2
2
1
2
1
2
2
1
2
2
1
2
2
1
2
1
2
2
1
Cycles
1
2
2
1+S
2+S
1+S
2+S
2+S
1
2
2
1+S
2+S
2+S
1+S
2+S
1+S
2+S
2+S
1+S


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