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PDF S3C7048 Data sheet ( Hoja de datos )

Número de pieza S3C7048
Descripción The S3C7044/C7048 single-chip CMOS microcontroller has been designed for very high-performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Ar
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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S3C7044/C7048/P7048
PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
The S3C7044/C7048 single-chip CMOS microcontroller has been designed for very high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
The S3P7048 is the microcontroller which has 8K-bytes one-time-programmable ROM and the functions are
same to S3C7044/C7048.
With two 8-bit timer/counters, an 8-bit serial I/O interface, and eight software n-channel open-drain I/O pins, the
S3C7044/C7048 offers an excellent design solution for a wide variety of general-purpose applications.
Up to 36 pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts
provide fast response to internal and external events.
In addition, the S3C7044/C7048's advanced CMOS technology provides for low power consumption and a wide
operating voltage range.
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S3C7048 pdf
S3C7044/C7048/P7048
PRODUCT OVERVIEW
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operation and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory access enable flags.
Before an interrupt is processed, the PSW is pushed onto the stack in data memory bank 0. When the routine is
completed, PSW values are restored.
IS1
IS0
EMB
ERB
C SC2 SC1 SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag ( C ) are 1- and 4-bit read/write or 8-bit read-only addressable. Skip condition flags (SC0–SC2) can be
addressed using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit location called the SB register store address values used to access specific memory and register
banks: the select memory bank register, SMB, and the select register bank register, SRB.
'SMB n' instructions select a data memory bank (0, 1, or 15) and store the upper four bits of the 12-bit data
memory address in the SMB register. The 'SMB n' instruction is used to select register bank 0, 1, 2, or 3, and to
store the address data in the SRB.
The instructions 'PUSH SB' and 'POP SB' move SMB and SRB values to and from the stack for interrupts and
subroutines.
CLOCK CIRCUITS
System oscillation circuit generates the internal clock signals for the CPU and peripheral hardwares. The system
clock can use a crystal, ceramic, or RC oscillation source, or an externally-generated clock signal. To drive
S3C7044/C7048 using an external clock source, the external clock signal should be input to Xin, and its inverted
signal to Xout.
A 4-bit power control register is used to enable or disable oscillation, and to select the CPU clock. The internal
system clock signal (fx) can be divided internally to produce three CPU clock frequencies fx/4, fx/8, or fx/64.
INTERRUPTS
Interrupt requests can be generated internally by on-chip processes (INTB, INTT0, INTT1, and INTS) or
externally by peripheral devices (INT0, INT1, and INT4). There are two quasi-interrupts: INT2 and INTW.
INT2/KS0–KS7 detects rising/falling edges of incoming signals and INTW detects time intervals of 0.5 seconds
of 3.91 milliseconds at 4.19MHz. The following components support interrupt processing:
Interrupt enable flags
Interrupt request flags
Interrupt priority registers
Power-down termination circuit
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S3C7048 arduino
S3C7044/C7048/P7048
PRODUCT OVERVIEW
Table 1-1. S3C7044/C7048 Pin Descriptions (Continued)
Pin Name Pin Type
Description
SCK
SO
SI
BTCO
INT0, INT1
INT2
INT4
TCLO0
TCLO1
CLO
BUZ
TCL0
TCL1
KS0–KS3
KS4–KS7
I/O Serial I/O interface clock signal
I/O Serial data output
I/O Serial data input
I/O Basic timer clock output (2 Hz, 16 Hz, 64 Hz, or 256
Hz at 4.19 MHz)
I External interrupts. The triggering edge for INT0 and
INT1 is selectable. INT0 is synchronized to system
clock.
I Quasi-interrupt with detection of rising edges
I External interrupt with detection of rising and falling
edges.
I/O Timer/counter 0 clock output
I/O Timer/counter 1 clock output
I/O Clock output
I/O 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at
4.19 MHz for buzzer sound
I/O External clock input for timer/counter 0
I/O External clock input for timer/counter 1
I/O Quasi-interrupt inputs with falling edge detection
VDD
– Power supply
VSS – Ground
RESET
I Reset signal
Xin, Xout
TEST
– Crystal, ceramic, or RC oscillator signal for system
clock (For external clock input, use Xin and input
Xin's reverse phase to Xout)
– Test signal input (must be connected to VSS)
NC – No connection (must be connected to VSS)
NOTE: Parentheses indicate pin number for 44 QFP package.
Number
12 (28)
11 (27)
10 (26)
9 (25)
Share
Pin
P0.0
P0.1
P0.2
P0.3
4, 3 P1.0, P1.1
(20, 19)
2 (18)
1 (17)
P1.2
P1.3
8 (24)
7 (23)
6 (22)
5 (21)
P2.0
P2.1
P2.2
P2.3
20 (38)
19 (37)
37–34
(11–8)
41–38
(15–12)
21 (39)
42 (16)
31 (5)
33, 32
(7, 6)
P3.0
P3.1
P6.0–P6.3
P7.0–P7.3
22 (40)
(33, 34)
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