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PDF S3C4510B Data sheet ( Hoja de datos )
| Número de pieza | S3C4510B | |
| Descripción | Samsungs S3C4510B 16/32-bit RISC microcontroller is a cost-effective/ high-performance microcontroller solution for Ethernet-based systems. | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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S3C4510B
PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
OVERVIEW
Samsung's S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller
solution for Ethernet-based systems. An integrated Ethernet controller, the S3C4510B, is designed for use in
managed communication hubs and routers.
The S3C4510B is built around an outstanding CPU core: the 16/32-bit ARM7TDMI RISC processor designed by
Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general purpose microprocessor macro-cell
that was developed for use in application-specific and custom-specific integrated circuits. Its simple, elegant, and
fully static design is particularly suitable for cost-sensitive and power-sensitive applications.
The S3C4510B offers a configurable 8K-byte unified cache/SRAM and Ethernet controller which reduces total
system cost. Most of the on-chip function blocks have been designed using an HDL synthesizer and the
S3C4510B has been fully verified in Samsung's state-of-the-art ASIC test environment.
Important peripheral functions include two HDLC channels with buffer descriptor, two UART channels, 2-channel
GDMA, two 32-bit timers, and 18 programmable I/O ports. On-board logic includes an interrupt controller, DRAM/
SDRAM controller, and a controller for ROM/SRAM and flash memory. The System Manager includes an internal
32-bit system bus arbiter and an external memory controller.
The following integrated on-chip functions are described in detail in this user's manual:
— 8K-byte unified cache/SRAM
— I2C interface
— Ethernet controller
— HDLC
— GDMA
— UART
— Timers
— Programmable I/O ports
— Interrupt controller
1-1
1 page  
S3C4510B
PRODUCT OVERVIEW
VDD
VSS
nUADTR1
UATXD1
nUADSR1
nDTRA
RXDA
nRTSA
TXDA
nCTSA
VDD
VSS
nDCDA
RXCA
nSYNCA
TXCA
nDTRB
RTDB
nRTSB
TXDB
VDD
VSS
nCTSB
nDCDB
RXCB
nSYNCB
TXCB
CRS/CRS_ 10M
RX DV/LINK_10M
RXD<0>/RXD_10M
VDD
VSS
RXD<1>
RXD<2>
RXD<3>
RX ERR
RX_CLK/RXCLK_10M
COL/COL_10M
TXD<0>/TXD_10M
TXD<1>/LOOP_10M
VDD
VSS
TXD<2>
TXD<3>
TX_ERR/POCMP_10M
TX_CLK/TXCLK_10M
TX_EN/TXEN_10M
MDIO
LITTLE
MDC
VDD
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
S3C4510B
208-QFP
156 VDD
155 VSS
154 XDATA<16>
153 XDATA<15>
152 XDATA<14>
151 XDATA<13>
150 XDATA<12>
149 XDATA<11>
148 XDATA<10>
147 XDATA<9>
146 XDATA<8>
145 XDATA<7>
144 XDATA<6>
143 VSS
142 VDD
141 XDATA<5>
140 XDATA<4>
139 XDATA<3>
138 XDATA<2>
137 XDATA<1>
136 XDATA<0>
135 XDATA<21>
134 XDATA<20>
133 XDATA<19>
132 XDATA<18>
131 VSS
130 VDD
129 ADDR<17>
128 ADDR<16>
127 ADDR<15>
126 ADDR<14>
125 ADDR<13>
124 ADDR<12>
123 ADDR<11>
122 ADDR<10>/AP
121 ADDR<9>
120 ADDR<8>
119 VSS
118 VDD
117 ADDR<7>
116 ADDR<6>
115 ADDR<5>
114 ADDR<4>
113 ADDR<3>
112 ADDR<2>
111 ADDR<1>
110 ADDR<0>
109 ExtMACK
108 ExtMREQ
107 nWBE<3>/DQM<3>
106 VSS
105 VDD
Figure 1-2. S3C4510B Pin Assignment Diagram
1-5
5 Page 
S3C4510B
Signal
nDTRB
nRTSB
nCTSB
nDCDB
nSYNCB
RXCB
TXCB
UCLK
UARXD0
UATXD0
nUADTR0
nUADSR0
UARXD1
UATXD1
nUADTR1
nUADSR1
P[7:0]
XINTREQ[3:0]
P[11:8]
nXDREQ[1:0]/
P[13:12]
nXDACK[1:0]
P[15:14]
TOUT0/P[16]
TOUT1/P[17]
SCL
SDA
PRODUCT OVERVIEW
Table 1-1. S3C4510B Signal Descriptions (Continued)
Pin No.
17
19
23
24
26
25
27
64
202
204
203
205
206
4
3
5
185–179,
176
191–189,
186
193, 192
195, 194
196
199
200
201
Type
O
O
I
I
O
I
I/O
I
I
O
I
O
I
O
I
O
I/O
Description
HDLC Ch-B data terminal ready. See the nDTRA pin description.
HDLC Ch-B request to send. See the nRTSA pin description.
HDLC Ch-B clear to send. See the nCTSA pin description.
HDLC Ch-B data carrier detected. See the nDCDA pin
description.
HDLC Ch-B sync is detected. See the nSYNCA pin description.
HDLC Ch-B receiver clock. See the RXCA pin description.
HDLC Ch-B transmitter clock. See the TXCA pin description.
The external UART clock input. MCLK or PLL generated clock
can be used as the UART clock. You can use UCLK, with an
appropriate divided by factor, if a very precious baud rate clock is
required.
UART0 receive data. RXD0 is the UART 0 input signal for
receiving serial data.
UART0 transmit data. TXD0 is the UART 0 output signal for
transmitting serial data.
Not UART0 data terminal ready. This input signals the S3C4510B
that the peripheral (or host) is ready to transmit or receive serial
data.
Not UART0 data set ready. This output signals the host
(or peripheral) that UART 0 is ready to transmit or receive serial
data.
UART1 receive data. See the RXD0 pin description.
UART1 transmit data. See the TXD0 pin description.
Not UART1 data terminal ready. See the DTR0 pin description.
Not UART1 data set ready. See the DSR0 pin description.
General I/O ports. See the I/O ports, chapter 12.
I/O External interrupt request lines or general I/O ports.
See the I/O ports, chapter 12.
I/O Not external DMA requests for GDMA or general I/O ports.
See the I/O ports, chapter 12.
I/O Not external DMA acknowledge from GDMA or general I/O ports.
See the I/O ports, chapter 12.
I/O Timer 0 out or general I/O port. See the I/O ports, chapter 12.
I/O Timer 1 out or general I/O port. See the I/O ports, chapter 12.
I/O I2C serial clock.
I/O I2C serial data.
1-11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet S3C4510B.PDF ] | |
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