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PDF S3C2440X Data sheet ( Hoja de datos )

Número de pieza S3C2440X
Descripción 16/32-bit RISC microprocessor
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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S3C2440X RISC MICROPROCESSOR
2003.10.15
PRODUCT OVERVIEW
PRODUCT OVERVIEW
INTRODUCTION
This manual describes SAMSUNG's S3C2440X 16/32-bit RISC microprocessor. SAMSUNG’s S3C24440X is
designed to provide hand-held devices and general applications with low-power, and high-performance micro-
controller solution in small die size. To reduce total system cost, the S3C2440X includes the following components
separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller
(STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART,
4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, Camera
interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-
ch SPI and PLL for clock generation.
The S3C2440X has been developed using an ARM920T core, 0.13um CMOS standard cells and a memory
complier. Its low-power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive
applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).
The S3C2440X offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by
Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture
with separate 16KB instruction and 16KB data caches, each with an 8-word line length.
By providing a complete set of common system peripherals, the S3C2440X minimizes overall system costs and
eliminates the need to configure additional components. The integrated on-chip functions that are described in this
document include:
1.2V internal, 1.8V/2.5V/3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB D-
Cache/MMU
External memory controller (SDRAM Control and Chip Select logic)
LCD controller (up to 4K color STN and 256K color TFT) with 1-ch LCD-dedicated DMA
4-ch DMAs with external request pins
3-ch UART (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO) / 2-ch SPI
1-ch multi-master IIC-BUS/1-ch IIS-BUS controller
SD Host interface version 1.0 & Multi-Media Card Protocol version 2.11 compatible
2-port USB Host /1- port USB Device (ver 1.1)
4-ch PWM timers & 1-ch internal timer
Watch Dog Timer
130-bit general purpose I/O ports / 24-ch external interrupt source
Power control: Normal, Slow, Idle and Sleep mode
8-ch 10-bit ADC and Touch screen interface
RTC with calendar function
On-chip clock generator with PLL
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
1-1

1 page




S3C2440X pdf
S3C2440X
2003.10.15
PRODUCT OVERVIEW
BLOCK DIAGRAM
ARM920T
IPA[31:0]
Instruction
MMU
IV2A[31:0]
C13
Instruction
CACHE
(16KB)
ID[31:0]
JTAG
ARM9TDMI
Processor core
(Internal Embedded ICE)
CP15
DD[31:0]
DV2A[31:0]
Data
MMU
DVA[31:0]
C13
DPA[31:0]
Data
CACHE
(16KB)
External
Coproc
Interface
Write
Buffer
AMBA
Bus
I/F
WriteBack WBPA[31:0]
PA Tag
RAM
LCD LCD
CONT. DMA
USB Host CONT.
ExtMaster
NAND Ctrl.
NAND Flash Boot
Loader
A
H
B
B
U
S
BUS CONT.
Arbitor/Decode
Interrupt CONT.
Power
Management
Camera
Interface
Memory CONT.
SRAM/NOR/SDRAM
Clock Generator
(MPLL)
Bridge & DMA (4Ch)
UART 0, 1, 2
I2C
USB Device
SDI/MMC
A
P
B
I2S
GPIO
Watchdog
Timer
BUS CONT.
Arbitor/Decode
B
U
S
RTC
ADC
SPIS0P,I1
Timer/PWM
0 ~ 3, 4(Internal)
Figure 1-1. S3C2440X Block Diagram
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
1-5

5 Page





S3C2440X arduino
S3C2440X
2003.10.15
PRODUCT OVERVIEW
Pin
Number
P16
H6
G3
H5
H4
H3
H7
J8
H2
G5
G7
G2
J3
J4
D12
C12
E11
A13
F10
F11
C13
A14
D13
B15
A17
C14
D15
C15
D14
B17
C16
E15
E14
Table 1-2. S3C2440X 289-Pin FBGA Pin Assignments (Sheet 2 of 9)
Pin
Name
XP/AIN7
CAMDATA0/GPJ0
CAMDATA1/GPJ1
CAMDATA2/GPJ2
CAMDATA3/GPJ3
CAMDATA4/GPJ4
CAMDATA5/GPJ5
CAMDATA6/GPJ6
CAMDATA7/GPJ7
CAMPCLK/GPJ8
CAMVSYNC/GPJ9
CAMHREF/GPJ10
CAMPCLKOUT/GPJ11
CAMRESET/GPJ12
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
Default
Function
XP
GPJ0
GPJ1
GPJ2
GPJ3
GPJ4
GPJ5
GPJ6
GPJ7
GPJ8
GPJ9
GPJ10
GPJ11
GPJ12
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
I/O State
@BUS REQ
–/–
–/–
–/–
–/–
–/–
–/–
–/–
–/–
–/–
–/–
–/–
–/–
–/–
–/–
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
I/O State
@Sleep
–/–
Hi-z/–
Hi-z/–
Hi-z/–
Hi-z/–
Hi-z/–
Hi-z/–
Hi-z/–
Hi-z/–
Hi-z/–
Hi-z/–
Hi-z/–
O(L)/–
O(L)/–
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
Hi-z,O(L)
I/O State
@nRESET
AI
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O Type
r10
t8
t8
t8
t8
t8
t8
t8
t8
t8
t8
t8
t8
t8
b12s
b12s
b12s
b12s
b12s
b12s
b12s
b12s
b12s
b12s
b12s
b12s
b12s
b12s
b12s
b12s
b12s
b12s
b12s
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
1-11

11 Page







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