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Número de pieza | S3C1860 | |
Descripción | 4-bit single-chip CMOS microcontroller | |
Fabricantes | Samsung semiconductor | |
Logotipo | ||
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No Preview Available ! 1. S3C1840
1 page S3C1840
PIN CONFIGURATION (20 DIP, 20 SOP)
VSS
XI
XO
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P3.3
1 20
2 19
3 18
4 17
5 S3C1840 16
6 15
7 14
8 13
9 12
10 11
VDD
P2.0/REM
TEST
P2.1
P2.2
P2.3
P2.4
P3.0
P3.1
P3.2
Figure 1-3. Pin Configuration (20 DIP, 20 SOP)
Table 1-2. Pin Description for 20 Pins
Pin
Name
P0.0-P0.3
P1.0-P1.1
P2.0/REM
P2.2-P2.4
P2.1
P3.0-P3.3
TEST
XI
XO
VDD
VSS
Pin
Number
4, 5, 6, 7
8, 9
19
16, 15, 14
17
13, 12, 11, 10
18
2
3
20
1
Pin
Type
Input
Input
Output
Output
Description
4-bit input port when P2.13 is low
2-bit input port when P2.13 is high
1-bit individual output for remote carrier
frequency (1)
1-bit individual output port
Output
Input
Input
Output
–
–
4-bit parallel output port
Input pin for test (Normally connected to VSS)
Oscillation clock input
Oscillation clock output
Power supply
Ground
I/O Circuit
Type
A
A
B
C
D
C
–
–
–
–
–
NOTES:
1. The carrier can be selected by software as fxx/12 (1/3 duty), fxx/12 (1/4 duty), fxx/8 (1/2 duty), or no-carrier
frequency.
2 Package type can be selected as 20 DIP, or 20 SOP in the ordering sheet.
1-4
5 Page S3C1840
DATA MEMORY (RAM)
The S3C1840's data memory consists of a 32-nibble RAM which is organized into two files of 16 nibbles each
(See Figure 1-11).
RAM addressing is implemented by a 7-bit register, HL.
It's upper 3-bit register (H) selects one of two files and its lower 4-bit register (L) selects one of 16 nibbles in the
selected file.
Instructions which manipulate the H and L registers are as follow:
Select a file :
MOV
NOT
H,#n
H
; H ← #n, where n must be 0,4
; Complement MSB of H register
Select a nibble in a selected file :
MOV
MOV
MOV
INCS
DECS
L,A
L,A,@HL
L,#N
L
L
; L←A
; L ← M (H,L)
; L ← #n, where 0 ≤ n ≤ 0FH
; L←L+1
; L←L-1
HL
3-bit 4-bit
The 7-bit HL register pair points to one of the 32 nibbles.
H register selects one of two files; 0, 4
L register selects one of 16 nibbles; 0 to 0FH
After reset, the HL register pair becomes to unknown state.
RAM Address
00
0F
File 0
40
File 4
4F
: Not built-in chip
7F
Figure 1-11. S3C1840 Data Memory Map
1-10
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet S3C1860.PDF ] |
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