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PDF S3882 Data sheet ( Hoja de datos )
| Número de pieza | S3882 | |
| Descripción | Current Mode PWM Controller | |
| Fabricantes | AUK corp | |
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Hay una vista previa y un enlace de descarga de S3882 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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Semiconductor
S3882
Current Mode PWM Controller
Descriptions
The S3882 is fixed PWM controller for Off-line and DC-DC converter applications. The
internal circuits include UVLO, low start up current circuit, temperature compensated
reference, high gain error amplifier, current sensing comparator, and high current
totempole output for driving a power MOSFET.
Also S3882 provide low start up current below 0.3mA and short shutdown delay
Time typical 100nsec.
S3882 have UVLO threshold of 16V(on) and 10V(off).
.
Features
• Low start up current < 0.3mA
• Operating range up to 500KHz
• Cycle by cycle current limiting
• Under Voltage Lock Out with hysteresis
• Short shutdown delay time ; typical 100nsec
• High current totempole output
• Output swing limiting : 22V
Ordering Information
Type NO.
Marking
S3882
S3882
Package Code
SOP-8
Outline Dimensions
unit : mm
PIN Connections
1. Output / Compensation
2. Voltage feedback. Input
3. Current sense Input
4. Rt/Ct
5. GND
6. Output
7. Vcc
8. Vref
KSI-8008-001
1
1 page  
S3882
4. Current Sense Circuit
Iβ
Ipeak =
R(V pin 1 - 2V be )
3R x Rs
R
C
Rs
ER R O R
AMP
2R
R IV
1
COMP
CUR R ENT
3 S ENS E
CUR R ENT
S ENS E
CO MP A R A T O R
G ND
5
A normal operating conditions occurs when the power supply output is overloaded or if output voltage to 1.0V
Therefore the maximum peak switch current is lpk(max)=1.0V/Rs, and under the normal operating conditions the
peak inductor current controlled by the voltage at pin1.
5. Shutdown Techniques
4.7K
8 V REF
1 COMP
Shutdown of the S3882 can be
4.7K
5.00
3 ISENSE
accomplished by two methods;
either raise pin3 above 1V or pull
S HUT
DO W N
T O CUR R ENT
S ENS E R ES IS T O R
S HUT
DOW N
pin1 below a voltage two diodes
drops above ground. Either causes
the output of the PWM method
comparator to be high (refer to
block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after
the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be
accomplished by adding an SCR which turn off, allowing the SCR to reset.
KSI-8008-001
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet S3882.PDF ] | |
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