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PDF IDT7201LA25D Data sheet ( Hoja de datos )

Número de pieza IDT7201LA25D
Descripción CMOS ASYNCHRONOUS FIFO 256 x 9/ 512 x 9/ 1K x 9
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9, 1K x 9
IDT7200L
IDT7201LA
IDT7202LA
FEATURES:
• First-In/First-Out dual-port memory
• 256 x 9 organization (IDT7200)
• 512 x 9 organization (IDT7201)
• 1K x 9 organization (IDT7202)
• Low power consumption
— Active: 770mW (max.)
—Power-down: 2.75mW (max.)
• Ultra high speed—12ns access time
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• Pin and functionally compatible with 720X family
• Status Flags: Empty, Half-Full, Full
• Auto-retransmit capability
• High-performance CEMOStechnology
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-87531, 5962-89666,
5962-89863 and 5962-89536 are listed on this function
• Industrial temperature range (-40oC to +85oC) is
available, tested to military electrical specifications
DESCRIPTION:
The IDT7200/7201/7202 are dual-port memories that load
and empty data on a first-in/first-out basis. The devices use
Full and Empty flags to prevent data overflow and underflow
and expansion logic to allow for unlimited expansion capability
in both word size and depth.
The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the devices
through the use of the Write (W) and Read (R) pins.
The devices utilizes a 9-bit wide data array to allow for
control and parity bits at the user’s option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability
that allows for reset of the read pointer to its initial position
when RT is pulsed low to allow for retransmission from the
beginning of data. A Half-Full Flag is available in the single
device mode and width expansion modes.
The IDT7200/7201/7202 are fabricated using IDT’s high-
speed CMOS technology. They are designed for those
applications requiring asynchronous and simultaneous read/
writes in multiprocessing and rate buffer applications. Military
grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
W
WRITE
CONTROL
DATA INPUTS
(D 0 –D 8)
WRITE
POINTER
RAM
ARRAY
256 x 9
512 x 9
1024 x 9
READ
POINTER
R
READ
CONTROL
THREE-
STATE
BUFFERS
DATA OUTPUTS
(Q 0–Q8)
RS
RESET
LOGIC
FLAG
LOGIC
EF FL/RT
FF
EXPANSION
XI
LOGIC
XO/HF
2679 drw 01
The IDT logo is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.03
DECEMBER 1996
DSC-2679/7
1

1 page




IDT7201LA25D pdf
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1) (Continued)
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)
Military Com'l & Mil.
Military(2)
7200 L40
7201LA40
7202LA40
7200L50
7201LA50
7202LA50
7200L65
7201LA65
7202LA65
7200L80
7201LA80
7202LA80
7200L120
7201LA120
7202LA120
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tS Shift Frequency
— 20 — 15 — 12.5 — 10 — 7 MHz
tRC Read Cycle Time
50 — 65 — 80 — 100 — 140 — ns
tA Access Time
— 40 — 50 — 65 — 80 — 120 ns
tRR
tRPW
tRLZ
tWLZ
Read Recovery Time
Read Pulse Width(3)
Read Pulse Low to Data Bus at Low Z(4)
Write Pulse High to Data Bus at Low Z(4, 5)
10
40
5
10
— 15 — 15 — 20 — 20 — ns
— 50 — 65 — 80 — 120 — ns
— 10 — 10 — 10 — 10 — ns
— 15 — 15 — 20 — 20 — ns
tDV Data Valid from Read Pulse High
5
tRHZ Read Pulse High to Data Bus at High Z(4)
— 5 — 5 — 5 — 5 — ns
25 — 30 — 30 — 30 — 35 ns
tWC
tWPW
Write Cycle Time
Write Pulse Width(3)
50 — 65 — 80 — 100 — 140 — ns
40 — 50 — 65 — 80 — 120 — ns
tWR Write Recovery Time
10 — 15 — 15 — 20 — 20 — ns
tDS Data Set-up Time
20 — 30 — 30 — 40 — 40 — ns
tDH Data Hold Time
0 — 5 — 10 — 10 — 10 — ns
tRSC
tRS
tRSS
Reset Cycle Time
Reset Pulse Width(3)
Reset Set-up Time(4)
50 — 65 — 80 — 100 — 140 — ns
40 — 50 — 65 — 80 — 120 — ns
40 — 50 — 65 — 80 — 120 — ns
tRSR Reset Recovery Time
10 — 15 — 15 — 20 — 20 — ns
tRTC Retransmit Cycle Time
tRT Retransmit Pulse Width(3)
tRTS Retransmit Set-up Time(4)
50 — 65 — 80 — 100 — 140 — ns
40 — 50 — 65 — 80 — 120 — ns
40 — 50 — 65 — 80 — 120 — ns
tRTR Retransmit Recovery Time
10 — 15 — 15 — 20 — 20 — ns
tEFL Reset to Empty Flag Low
— 50 — 65 — 80 — 100 — 140 ns
tHFH,FFH Reset to Half-Full and Full Flag High
— 50 — 65 — 80 — 100 — 140 ns
tRTF Retransmit Low to Flags Valid
— 50 — 65 — 80 — 100 — 140 ns
tREF Read Low to Empty Flag Low
— 30 — 45 — 60 — 60 — 60 ns
tRFF Read High to Full Flag High
tRPE Read Pulse Width after EF High
— 35 — 45 — 60 — 60 — 60 ns
40 — 50 — 65 — 80 — 120 — ns
tWEF Write High to Empty Flag High
— 35 — 45 — 60 — 60 — 60 ns
tWFF Write Low to Full Flag Low
— 35 — 45 — 60 — 60 — 60 ns
tWHF Write Low to Half-Full Flag Low
— 50 — 65 — 80 — 100 — 140 ns
tRHF
tWPF
tXOL
tXOH
tXI
tXIR
tXIS
Read High to Half-Full Flag High
Write Pulse Width after FF High
Read/Write to XO Low
Read/Write to XO High
XI Pulse Width(3)
XI Recovery Time
XI Set-up Time
— 50 — 65 — 80 — 100 — 140 ns
40 — 50 — 65 — 80 — 120 — ns
— 40 — 50 — 65 — 80 — 120 ns
— 40 — 50 — 65 — 80 — 120 ns
40 — 50 — 65 — 80 — 120 — ns
10 — 10 — 10 — 10 — 10 — ns
10 — 15 — 15 — 15 — 15 — ns
NOTES:
1. Timings referenced as in AC Test Conditions
2. Speed grades 65, 80 and 120 not available in the CERPACK
3. Pulse widths less than minimum value are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
2679 tbl 07
5.03 5

5 Page





IDT7201LA25D arduino
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9
(HALF–FULL FLAG)
(HF)
WRITE (W)
DATA IN (D)
FULL FLAG (FF)
RESET (RS)
9
IDT
7200/
7201A/
7202A
MILITARY AND COMMERCIAL TEMPERATURE RANGES
READ (R)
9
DATA OUT (Q)
EMPTY FLAG (EF)
RETRANSMIT (RT)
EXPANSION IN (XI)
2679 drw 14
Figure 12. Block Diagram of Single 256/512/1024 x 9 FIFO
DATA IN (D)
WRITE (W)
FULL FLAG (FF)
RESET (RS)
18
9
HF
9
IDT
7200/
7201A/
7202A
9
HF
IDT
7200/
7201A/
7202A
9
READ (R)
EMPTY FLAG (EF)
RETRANSMIT (RT)
XI XI
18
DATA OUT (Q)
Figure 13. Block Diagram of 256/512/1024 x 18 FIFO Memory Used in Width Expansion Mode
2679 drw 15
TABLE I—RESET AND RETRANSMIT
Single Device Configuration/Width Expansion Mode
Mode
Reset
Retransmit
Read/Write
Inputs
RS RT
0X
10
11
XI
0
0
0
NOTE:
1. Pointer will increment if flag is High.
Internal Status
Read Pointer
Write Pointer
Location Zero
Location Zero
Location Zero
Increment(1)
Unchanged
Increment(1)
Outputs
EF FF
01
XX
XX
HF
1
X
X
2679 tbl 09
TABLE II—RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Mode
Inputs
Internal Status
RS FL
XI Read Pointer Write Pointer
Reset First Device
0
0
(1) Location Zero
Location Zero
Reset All Other Devices
0
1
(1) Location Zero
Location Zero
Read/Write
1 X (1)
X
X
Outputs
EF FF
01
01
XX
NOTE:
2679 tbl 10
1. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Flag Full Output,
XI = Expansion Input, HF = Half-Full Flag Output
5.03 11

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