PDF IDT7200L Data sheet ( Hoja de datos )

Número de pieza	IDT7200L
Descripción	CMOS ASYNCHRONOUS FIFO 256 x 9/ 512 x 9/ 1K x 9
Fabricantes	Integrated Device Technology
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No Preview Available ! CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9 IDT7200L IDT7201LA IDT7202LA FEATURES: • First-In/First-Out dual-port memory • 256 x 9 organization (IDT7200) • 512 x 9 organization (IDT7201) • 1,024 x 9 organization (IDT7202) • Low power consumption — Active: 440mW (max.) —Power-down: 28mW (max.) • Ultra high speed—12ns access time • Asynchronous and simultaneous read and write • Fully expandable by both word depth and/or bit width • 720x family is pin and functionally compatible from 256 x 9 to 64k x 9 • Status Flags: Empty, Half-Full, Full • Auto-retransmit capability • High-performance CEMOS™ technology • Military product compliant to MIL-STD-883, Class B • Standard Military Drawing #5962-87531, 5962-89666, 5962-89863 and 5962-89536 are listed on this function • Dual versions available in the TSSOP package. For more informa- tion, see IDT7280/7281/7282 data sheet IDT7280 = 2 x IDT7200 IDT7281 = 2 x IDT7201 IDT7282 = 2 x IDT7202 • Industrial temperature range (–40oC to +85oC) is available (plastic packages only) • Green parts available, see ordering information DESCRIPTION: The IDT7200/7201/7202 are dual-port memories that load and empty data onafirst-in/first-outbasis. ThedevicesuseFullandEmptyflagstopreventdata overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write (W) and Read (R) pins. The devices utilize a 9-bit wide data array to allow for control and parity bits at the user’s option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception errorchecking. ItalsofeaturesaRetransmit(RT)capabilitythatallowsforreset of the read pointer to its initial position when RT is pulsed LOW to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes. These FIFOs are fabricated using high-speed CMOS technology. They are designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Military grade product is manufactured in compliance with MIL-STD-883, Class B. FUNCTIONAL BLOCK DIAGRAM W WRITE CONTROL DATA INPUTS (D0-D8) WRITE POINTER RAM ARRAY 256 x 9 512 x 9 1,024 x 9 READ POINTER R READ CONTROL THREE- STATE BUFFERS DATA OUTPUTS (Q0-Q8) FLAG LOGIC EF FF EXPANSION XI LOGIC XO/HF IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES 1 ©2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. RS RESET LOGIC FL/RT 2679 drw 01 JUNE 2012 DSC-2679/14 1 page IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9 COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURERANGES AC ELECTRICAL CHARACTERISTICS(1) (Continued) (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C) Military IDT7200L30 IDT7201LA30 IDT7202LA30 Commercial IDT7200L35 IDT7201LA35 IDT7202LA35 Com'l & Mil.(2) IDT7200L50 IDT7201LA50 IDT7202LA50 Military(2) IDT7201LA80 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit tS ShiftFrequency — 25 — 22.2 — 15 — 10 MHz tRC Read Cycle Time 40 — 45 — 65 — 100 — ns tA AccessTime — 30 — 35 — 50 — 80 ns tRR ReadRecoveryTime 10 — 10 — 15 — 20 — ns tRPW ReadPulseWidth(3) 30 — 35 — 50 — 80 — ns tRLZ Read Pulse Low to Data Bus at Low Z(4) 3 — 3 — 3 — 3 — ns tWLZ Write Pulse High to Data Bus at Low Z(4,5) 5 — 5 — 5 — 5 — ns tDV Data Valid from Read Pulse High 5 — 5 — 5 — 5 — ns tRHZ Read Pulse High to Data Bus at High Z(4) — 20 — 20 — 30 — 30 ns tWC Write Cycle Time 40 — 45 — 65 — 100 — ns tWPW WritePulseWidth(3) 30 — 35 — 50 — 80 — ns tWR WriteRecoveryTime 10 — 10 — 15 — 20 — ns tDS DataSet-upTime 18 — 18 — 30 — 40 — ns tDH DataHoldTime 0 — 0 — 5 — 10 — ns tRSC Reset Cycle Time 40 — 45 — 65 — 100 — ns tRS ResetPulseWidth(3) 30 — 35 — 50 — 80 — ns tRSS ResetSet-upTime(4) 30 — 35 — 50 — 80 — ns tRSR ResetRecoveryTime 10 — 10 — 15 — 20 — ns tRTC RetransmitCycleTime 40 — 45 — 65 — 100 — ns tRT RetransmitPulseWidth(3) 30 — 35 — 50 — 80 — ns tRTS RetransmitSet-upTime(4) 30 — 35 — 50 — 80 — ns tRTR RetransmitRecoveryTime 10 — 10 — 15 — 20 — ns tEFL Reset to Empty Flag Low — 40 — 45 — 65 — 100 ns tHFH,FFH ResettoHalf-FullandFullFlagHigh — 40 — 45 — 65 — 100 ns tRTF RetransmitLowtoFlagsValid — 40 — 45 — 65 — 100 ns tREF Read Low to Empty Flag Low — 30 — 30 — 45 — 60 ns tRFF Read High to Full Flag High — 30 — 30 — 45 — 60 ns tRPE ReadPulseWidthafter EF High 30 — 35 — 50 — 80 — ns tWEF Write High to Empty Flag High — 30 — 30 — 45 — 60 ns tWFF Write Low to Full Flag Low — 30 — 30 — 45 — 60 ns tWHF Write Low to Half-Full Flag Low — 40 — 45 — 65 — 100 ns tRHF Read High to Half-Full Flag High — 40 — 45 — 65 — 100 ns tWPF WritePulseWidthafterFFHigh 30 — 35 — 50 — 80 — ns tXOL Read/Write to XO Low — 30 — 35 — 50 — 80 ns tXOH Read/Write to XO High — 30 — 35 — 50 — 80 ns tXI XI Pulse Width(3) 30 — 35 — 50 — 80 — ns tXIR XI Recovery Time 10 — 10 — 10 — 10 — ns tXIS XI Set-up Time 10 — 10 — 15 — 15 — ns NOTES: 1. Timings referenced as in AC Test Conditions 2. Military speed grades of 50ns and 80ns are only available for IDT7201LA. 3. Pulse widths less than minimum value are not allowed. 4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode. 5 5 Page IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9 COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURERANGES TABLE 1 — RESET AND RETRANSMIT Single Device Configuration/Width Expansion Mode Mode Inputs RS RT XI Internal Status Read Pointer Write Pointer Reset Retransmit Read/Write 0 X 0 LocationZero LocationZero 1 0 0 LocationZero Unchanged 1 1 0 Increment(1) Increment(1) NOTE: 1. Pointer will increment if flag is HIGH. Outputs EF FF 01 XX XX HF 1 X X TABLE 2 — RESET AND FIRST LOAD TRUTH TABLE Depth Expansion/Compound Expansion Mode Mode Inputs Internal Status RS FL XI Read Pointer Write Pointer Outputs EF FF Reset First Device Reset All Other Devices Read/Write 0 0 (1) LocationZero LocationZero 0 1 (1) LocationZero LocationZero 1 X (1) X X 01 01 XX NOTE: 1. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output W D FULL RS XO FF IDT EF R 7200/ 9 9 7201A/ 9Q 7202A FL VCC XI XO FF 9 IDT 7200/ 7201A/ 7202A EF FL EMPTY FF 9 XI XO IDT 7200/ 7201A/ 7202A XI EF FL 2678 drw16 Figure 14. Block Diagram of 768 x 9, 1,536 x 9, 3,072 x 9 FIFO Memory (Depth Expansion) 11 11 Page

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