PDF IDT71V632SA4PF Data sheet ( Hoja de datos )

Número de pieza	IDT71V632SA4PF
Descripción	64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter/ Single Cycle Deselect
Fabricantes	Integrated Device Technology
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No Preview Available ! 64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect IDT71V632 Features x 64K x 32 memory configuration x Supports high system speed: Commercial: – A4 4.5ns clock access time (117 MHz) Commercial and Industrial: – 5 5ns clock access time (100 MHz) – 6 6ns clock access time (83 MHz) – 7 7ns clock access time (66 MHz) x Single-cycle deselect functionality (Compatible with Micron Part # MT58LC64K32D7LG-XX) x LBO input selects interleaved or linear burst mode x Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) x Power down controlled by ZZ input x Operates with a single 3.3V power supply (+10/-5%) x Packaged in a JEDEC Standard 100-pin rectangular plastic thin quad flatpack (TQFP). Description The IDT71V632 is a 3.3V high-speed SRAM organized as 64K x 32 with full support of the Pentium™ and PowerPC™ processor interfaces. The pipelined burst architecture provides cost-effective 3-1-1-1 second- ary cache performance for processors up to 117MHz. The IDT71V632 SRAM contains write, data, address, and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the extreme end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V632 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these threeaddresseswillbedefinedbytheinternalburstcounterandthe LBO input pin. The IDT71V632 SRAM utilizes IDT's high-performance, high-volume 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board density in both desktop and notebook applications. Pin Description Summary A0–A15 Address Inputs CE Chip Enable CS0, CS1 Chips Selects OE Output Enable GW Global Write Enable BWE Byte Write Enable BW1, BW2, BW3, BW4 Individual Byte Write Selects CLK Clock ADV Burst Address Advance ADSC Address Status (Cache Controller) ADSP Address Status (Processor) LBO Linear / Interleaved Burst Order ZZ Sleep Mode I/O0–I/O31 Data Input/Output VDD, VDDQ 3.3V VSS, VSSQ Array Ground, I/O Ground Pentium processor is a trademark of Intel Corp. PowerPC is a trademark of International Business Machines, Inc. ©2000 Integrated Device Technology, Inc. 1 Input Input Input Input Input Input Input Input Input Input Input Input Input I/O Power Power Synchronous Synchronous Synchronous Asynchronous Synchronous Synchronous Synchronous N/A Synchronous Synchronous Synchronous DC Asynchronous Synchronous N/A N/A 3619 tbl 01 AUGUST 2001 DSC-3619/04 1 page IDT71V632, 64K x 32, 3.3V Synchronous SRAM with Pipelined Outputs and Single Cycle Deselect Pin Configuration Commercial and Industrial Temperature Ranges 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC I/O16 I/O17 VDDQ VSSQ I/O18 I/O19 I/O20 I/O21 VSSQ VDDQ I/O22 I/O23 VDD/NC(1) VDD NC VSS I/O24 I/O25 VDDQ VSSQ I/O26 I/O27 I/O28 I/O29 VSSQ VDDQ I/O30 I/O31 NC 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 PK100-1 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC I/O15 I/O14 VDDQ VSSQ I/O13 I/O12 I/O11 I/O10 VSSQ VDDQ I/O9 I/O8 VSS NC VDD ZZ(2) I/O7 I/O6 VDDQ VSSQ I/O5 I/O4 I/O3 I/O2 VSSQ VDDQ I/O1 I/O0 NC Top View TQFP NOTES: 1. Pin 14 can either be directly connected to VDD or not connected. 2. Pin 64 can be left unconnected and the device will always remain in active mode. 3619 drw 02 6.452 5 Page IDT71V632, 64K x 32, 3.3V Synchronous SRAM with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3) 6.1412 11 Page

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