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PDF IDT71V546S100PF Data sheet ( Hoja de datos )

Número de pieza IDT71V546S100PF
Descripción 128K x 36/ 3.3V Synchronous SRAM with ZBT Feature/ Burst Counter and Pipelined Outputs
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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128K x 36, 3.3V Synchronous
IDT71V546
SRAM with ZBTFeature,
Burst Counter and Pipelined Outputs
Features
x 128K x 36 memory configuration, pipelined outputs
x Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
x ZBTTM Feature - No dead cycles between write and read
cycles
x Internally synchronized registered outputs eliminate the
need to control OE
x Single R/W (READ/WRITE) control pin
x Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
x 4-word burst capability (interleaved or linear)
x Individual byte write (BW1 - BW4) control (May tie active)
x Three chip enables for simple depth expansion
x Single 3.3V power supply (±5%)
x Packaged in a JEDEC standard 100-pin TQFP package
Description
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to
eliminate dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Thus it has been given the name ZBTTM,
or Zero Bus Turn-around.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later its associated data cycle occurs, be it
read or write.
The IDT71V546 contains data I/O, address and control signal regis-
ters. Output enable is the only asynchronous signal and can be used to
disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V546 to be
suspended as long as necessary. All synchronous inputs are ignored
when CEN is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive
when ADV/LDis low, no new memory operation can be initiated and any
burst that was in progress is stopped. However, any pending data
transfers(readsorwrites)willbecompleted. Thedatabuswilltri-statetwo
cycles after the chip is deselected or a write initiated.
The IDT71V546 has an on-chip burst counter. In the burst mode, the
IDT71V546 can provide four cycles of data for a single address presented
totheSRAM. TheorderoftheburstsequenceisdefinedbytheLBOinput
pin. TheLBO pinselectsbetweenlinearandinterleavedburstsequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/LD = HIGH).
The IDT71V546 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for high board density.
Pin Description Summary
A0 - A16
CE1, CE2, CE2
OE
R/W
CEN
Address Inputs
Three Chip Enables
Output Enable
Read/Write Signal
Clock Enable
BW1, BW2, BW3, BW4 Individual Byte Write Selects
CLK
ADV/LD
Clock
Advance Burst Address / Load New Address
LBO Linear / Interleaved Burst Order
I/O0 - I/O31, I/OP1 - I/OP4 Data Input/Output
VDD 3.3V Power
VSS Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Static
Static
3821 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
1
©1999 Integrated Device Technology, Inc.
DECEMBER 1999
DSC-3821/03

1 page




IDT71V546S100PF pdf
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBTFeature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1)
CEN R/W
Chip(5)
Enable
ADV/LD
BWx
ADDRESS
USED
PREVIOUIS CYCLE
CURRENT CYCLE
I/O
(2 cycles later)
L L Select L Valid External
X
LOAD WRITE
D(7)
L H Select
L
X External
X
LOAD READ
Q(7)
LX
X
H
Valid Internal
LOAD WRITE/
BURST WRITE
D(7)
BURST WRITE
(Advance Burst Counter)(2)
LX
X
H
X Internal
LOAD READ/
BURST READ
Q(7)
BURST READ
(Advance Burst Counter)(2)
L X Deselect
L
X
X
X
DESELECT or STOP(3)
HiZ
LX
HX
X
X
H X X DESELECT / NOOP
NOOP
HiZ
XXX
X
SUSPEND(4)
Previous Value
NOTES:
3821 tbl 07
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if either one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
Operation
R/W BW1 BW2 BW3 BW4
READ
HX X X X
WRITE ALL BYTES
LLLLL
WRITE BYTE 1 (I/O [0:7], I/OP1)(2)
L
L
H
H
H
WRITE BYTE 2 (I/O [8:15], I/OP2)(2)
L
H
L
H
H
WRITE BYTE 3 (I/O [16:23], I/OP3)(2)
L
H
H
L
H
WRITE BYTE 4 (I/O [24:31], I/OP4)(2)
L
H
H
H
L
NO WRITE
L HHHH
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3821 tbl 08
6.452

5 Page





IDT71V546S100PF arduino
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBTFeature, Burst Counter and Pipelined Outputs
Read Operation With Chip Enable Used(1)
Cycle
Address
R/W ADV/LD CE(1) CEN BWx
Commercial and Industrial Temperature Ranges
OE I/O
Comments
n X X L H L X X ? Deselected
n+1 X X L H L X X ? Deselected
n+2 A0 H L L L X X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP
n+4 A1 H L L L X L Q0 Address A0 read out. Load A1
n+5 X X L H L X X Z Deselected or STOP
n+6 X X L H L X L Q1 Address A1 Read out. Deselected
n+7 A2 H L L L X X Z Address and Control meet setup
n+8 X X L H L X X Z Deselected or STOP
n+9 X X L H L X L Q2 Address A2 read out. Deselected
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
3821 tbl 18
Write Operation With Chip Enable Used(1)
Cycle
Address
R/W ADV/LD CE(1) CEN BWx
n X X L HLX
n+1 X X L H L X
n+2 A0 L L L L L
n+3 X X L H L X
n+4 A1 L L L L L
n+5 X X L H L X
n+6 X X L H L X
n+7 A2 L L L L L
n+8 X X L H L X
n+9 X X L H L X
OE
X
X
X
X
X
X
X
X
X
X
I/O Comments
? Deselected
? Deselected
Z Address and Control meet setup
Z Deselected or STOP
D0 Address D0 Write In. Load A1
Z Deselected or STOP
D1 Address D1 Write In. Deselected
Z Address and Control meet setup
Z Deselected or STOP
D2 Address D2 Write In. Deselected
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3821 tbl 19
6.1412

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