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PDF IDT71V35761SA183BQ Data sheet ( Hoja de datos )

Número de pieza IDT71V35761SA183BQ
Descripción 128K x 36/ 256K x 18 3.3V Synchronous SRAMs 3.3V I/O/ Pipelined Outputs Burst Counter/ Single Cycle Deselect
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! IDT71V35761SA183BQ Hoja de datos, Descripción, Manual

128K x 36, 256K x 18
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
IDT71V35761S
IDT71V35781S
IDT71V35761SA
IDT71V35781SA
Features
x 128K x 36, 256K x 18 memory configurations
x Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
Commercial and Industrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
x LBO input selects interleaved or linear burst mode
x Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
x 3.3V core power supply
x Power down controlled by ZZ input
x 3.3V I/O
x Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
x Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
Pin Description Summary
Description
The IDT71V35761/781 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V35761/781 SRAMs contain write, data,
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V35761/81 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
datawillbeavailabletotheuseronthenextthreerisingclockedges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V35761/781 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array.
A0-A17
Address Inputs
Input Synchronous
CE Chip Enable
Input Synchronous
CS0, CS1
Chip Selects
Input Synchronous
OE Output Enable
Input Asynchronous
GW Global Write Enable
Input Synchronous
BWE Byte Write Enable
Input Synchronous
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
Input Synchronous
CLK Clock
Input N/A
ADV Burst Address Advance
Input Synchronous
ADSC
Address Status (Cache Controller)
Input Synchronous
ADSP
Address Status (Processor)
Input Synchronous
LBO Linear / Interleaved Burst Order
Input DC
TMS Test Mode Select
Input Synchronous
TDI Test Data Input
Input Synchronous
TCK Test Clock
Input N/A
TDO Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input Asynchronous
ZZ Sleep Mode
Input Asynchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
N/A
NVOSTSE:
Ground
1. BW3 and BW4 are not applicable for the IDT71V35781.
©2003 Integrated Device Technology, Inc.
1
Supply
N/A
5301 tbl 01
JUNE 2003
DSC-5301/03

1 page




IDT71V35761SA183BQ pdf
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VDD / NC(1)
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ(2)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
,
5301drw 02
100 TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.452

5 Page





IDT71V35761SA183BQ arduino
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1, 2)
Operation
GW BWE BW1 BW2 BW3 BW4
Read
HHX X X X
Read
HL HHHH
Write all Bytes L X X X X X
Write all Bytes H L L L L L
Write Byte 1(3) H L L H H H
Write Byte 2(3) H L H L H H
Write Byte 3(3) H L H H L H
Write Byte 4(3) H L H H H L
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V35781.
3. Multiple bytes may be selected during the same cycle.
5301 tbl 12
Asynchronous Truth Table(1)
Operation(2)
OE
ZZ
I/O Status
Power
Read
LL
Data Out
Active
Read
HL
High-Z
Active
Write
XL
High-Z – Data In
Active
Deselected
XL
High-Z
Standby
Sleep Mode
XH
High-Z
Sleep
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
5301 tbl 13
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address
0 0 0 1 10 1 1
Second Address
0 10 0 1 1 10
Third Address
10 1100 0 1
Fourth Address(1)
1 1100 100
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
5301 tbl 14
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
A1 A0 A1 A0
First Address
000 1
Second Address
0 110
Third Address
10 11
Fourth Address(1)
1 10 0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.1412
Sequence 3
A1 A0
10
11
00
01
Sequence 4
A1 A0
11
00
01
10
5301 tbl 15

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