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PDF IDT71V321S Data sheet ( Hoja de datos )

Número de pieza IDT71V321S
Descripción HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
HIGH-SPEED 3.3V
2K x 8 DUAL-PORT
STATIC RAM WITH INTERRUPT
IDT71V321S/L
FEATURES:
• High-speed access
—Commercial: 25/35/55ns (max.)
• Low-power operation
—IDT71V321S
—Active: 250mW (typ.)
—Standby: 3.3mW (typ.)
—IDT71V321L
—Active: 250mW (typ.)
—Standby: 660µW (typ.)
• Two INT flags for port-to-port communications
• On-chip port arbitration logic
BUSY output flag
• Fully asynchronous operation from either port
• Battery backup operation—2V data retention
• TTL-compatible, single 3.3V ±0.3V power supply
• Available in popular plastic packages
DESCRIPTION:
The IDT71V321 is a high-speed 2K x 8 Dual-Port Static
RAMs with internal interrupt logic for interprocessor com-
munications. The IDT71V321 is designed to be used as a
stand-alone 8-bit Dual-Port RAM.
The device provides two independent ports with sepa-
rate control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE, permits the on chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT's CMOS high-performance technol-
ogy, these devices typically operate on only 250mW of
power. Low-power (L) versions offer battery backup data
retention capability, with each Dual-Port typically consum-
ing 200µW from a 2V battery.
The IDT71V321 devices are packaged in a 52-pin PLCC
and a 64-pin TQFP (thin plastic quad flatpack).
FUNCTIONAL BLOCK DIAGRAM
OEL
WCEL
R/ L
OER
WCER
R/ R
I/O0L- I/O7L
BUSYL(1,2)
A10L
A0L
NOTE:
1. BUSY and INT
are totem-pole
outputs.
I/O
Control
I/O
Control
Address
Decoder
CEL
OEL
WR/ L
11
MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
11
CER
WOER
R/ R
(2)
INTL
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.34
I/O0R-I/O7R
BUSYR(1,2)
A10R
A0R
(2)
INTR
3026 drw 01
OCTOBER 1996
DSC-3026/2
1

1 page




IDT71V321S pdf
IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Figures 1and 2
3026 tbl 08
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
3.0V
VDR 2.0V
3.0V
tCDR
tR
CE VDR
VIH VIH
3026 drw 04
DATA OUT
BUSY
INT 435
3.3V
590
30pF
Figure 1. AC Output Test Load
DATA OUT
435
3.3V
590
5pF
3026 drw 05
Figure 2. Output Test Load
(For tHZ, tLZ, tWZ and tOW)
* Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3)
71V321X25
71V321X35
71V321X55
Symbol
Parameter
Min. Max. Min.
READ CYCLE
tRC Read Cycle Time
25 — 35
tAA Address Access Time
— 25 —
tACE Chip Enable Access Time
— 25 —
tAOE Output Enable Access Time
— 12 —
tOH Output Hold from Address Change
3—3
tLZ Output Low-Z Time(1, 2)
0—0
tHZ Output High-Z Time(1, 2)
— 12 —
tPU Chip Enable to Power Up Time(2)
0—0
tPD Chip Disable to Power Down Time(2)
— 50 —
NOTES:
1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. "X" in part numbers indicates power rating (S or L).
Max. Min.
— 55
35 —
35 —
20 —
—3
—0
15 —
—0
50 —
Max. Unit
— ns
55 ns
55 ns
25 ns
— ns
— ns
30 ns
— ns
50 ns
3026 tbl 09
6.34 5

5 Page





IDT71V321S arduino
IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
71V321X25
71V321X35
Symbol
Parameter
INTERRUPT TIMING
tAS Address Set-up Time
tWR Write Recovery Time
tINS Interrupt Set Time
tINR Interrupt Reset Time
NOTE:
1. "X" in part numbers indicates power rating (S or L).
Min. Max. Min. Max.
0—
0—
— 25
— 25
0—
0—
— 25
— 25
71V321X55
Min. Max. Unit
0 — ns
0 — ns
— 45 ns
— 45 ns
3026 tbl 12
TIMING WAVEFORM OF INTERRUPT MODE
INT SETS
ADDR'A'
WR/ 'A'
INT'B'
tWC
INTERRUPT ADDRESS(2)
tAS(3)
tWR(4)
tINS(3)
INT CLEARS
ADDR'B'
OE'B'
INT'A'
tRC
INTERRUPT CLEAR ADDRESS
tAS (3)
tINR (3)
NOTES:.
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
3026 drw 14
3026 drw 15
6.34 11

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