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PDF IDT71V30L55TFI Data sheet ( Hoja de datos )

Número de pieza IDT71V30L55TFI
Descripción HIGH-SPEED 3.3V 1K X 8 DUAL-PORT STATIC RAM
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! IDT71V30L55TFI Hoja de datos, Descripción, Manual

HIGH-SPEED 3.3V
1K X 8 DUAL-PORT
STATIC RAM
IDT71V30S/L
Features
x High-speed access
– Commercial: 25/35/55ns (max.)
x Low-power operation
– IDT71V30S
Active: 375mW (typ.)
Standby: 5mW (typ.)
– IDT71V30L
Active: 375mW (typ.)
Standby: 1mW (typ.)
x On-chip port arbitration logic
x Interrupt flags for port-to-port communication
x Fully asynchronous operation from either port
x Battery backup operation, 2V data retention (L Only)
x TTL-compatible, single 3.3V ±0.3V power supply
x Industrial temperature range (-40OC to +85OC) is available
for selected speeds
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL(1)
A9L
A0L
I/O
Control
I/O
Control
Address
Decoder
10
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
10
CER
OER
R/WR
INTL(2)
NOTES:
1. IDT71V30: BUSY outputs are non-tristatable push-pulls.
2. INT outputs are non-tristable push-pull output structure.
I/O0R-I/O7R
BUSYR(1)
A9R
A0R
INTR(2)
3741 drw 01
©2000 Integrated Device Technology, Inc.
1
JANUARY 2001
DSC 3741/7

1 page




IDT71V30L55TFI pdf
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
3741 tbl 08
Industrial and Commercial Temperature Ranges
Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
VDR 2.0V
3.0V
tCDR
tR
CE VDR
VIH VIH
3741 drw 04 ,
DATA OUT
BUSY
INT
435
3.3V
590
30pF
Figure 1. AC Output Test Load
DATA OUT
435
3.3V
590
5pF
3741 drw 05
Figure 2. Output Test Load
(For tHZ, tLZ, tWZ and tOW)
* Including scope and jig.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(3,4)
71V30X25
Com'l Only
71V30X35
Com'l Only
Symbol
Parameter
Min. Max. Min. Max.
READ CYCLE
tRC Read Cycle Time
25 ____ 35 ____
tAA Address Access Time
____ 25 ____ 35
tACE Chip Enable Access Time
____ 25 ____ 35
tAOE Output Enable Access Time
____ 12 ____ 20
tOH Output Hold from Address Change
3 ____ 3 ____
tLZ Output Low-Z Time(1,2)
0 ____ 0 ____
tHZ Output High-Z Time(1,2)
____ 12 ____ 15
tPU Chip Enable to Power Up Time (2)
0 ____ 0 ____
tPD Chip Disable to Power Down Time(2)
____ 50 ____ 50
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part number indicates power rating (S or L).
4. Industrial temperature: for specific speeds, packages and power contact your sales office.
71V30X55
Com'l Only
Min. Max.
Unit
55 ____ ns
____ 55 ns
____ 55 ns
____ 25 ns
3 ____ ns
0 ____ ns
____ 30 ns
0 ____ ns
____ 50 ns
3741 tbl 09
6.542

5 Page





IDT71V30L55TFI arduino
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2)
71V30X25
Com'l Only
71V30X35
Com'l Only
71V30X55
Com'l Only
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
INTERRUPT TIMING
tAS Address Set-up Time
0 ____ 0 ____ 0 ____ ns
tWR Write Recovery Time
0 ____ 0 ____ 0 ____ ns
tINS Interrupt Set Time
____ 25 ____ 25 ____ 45 ns
tINR Interrupt Reset Time
____ 25 ____ 25 ____ 45 ns
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
3741 tbl 12
Timing Waveform of Interrupt Mode(1)
INT Sets
tWC
ADDR'A'
INTERRUPT ADDRESS (2)
tAS (3)
tWR(4)
R/W'A'
INT'B'
tINS (3)
INT Clears
ADDR'B'
OE'B'
INT'A'
tRC
INTERRUPT CLEAR ADDRESS
tAS (3)
tINR (3)
NOTES:.
1. All timing is the same for left and right ports. Port Amay be either left or right port. Port Bis the opposite from port A.
2. See Interrupt Truth Table II.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
3741 drw 14
3741 drw 15
61.412

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