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PDF IDT71V2576YSA133PFI Data sheet ( Hoja de datos )

Número de pieza IDT71V2576YSA133PFI
Descripción 128K X 36/ 256K X 18 3.3V Synchronous SRAMs 2.5V I/O/ Pipelined Outputs/ Burst Counter/ Single Cycle Deselect
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! IDT71V2576YSA133PFI Hoja de datos, Descripción, Manual

128K X 36, 256K X 18
3.3V Synchronous SRAMs
2.5V I/O, Pipelined Outputs,
Burst Counter, Single Cycle Deselect
IDT71V2576S
IDT71V2578S
IDT71V2576SA
IDT71V2578SA
Features
x 128K x 36, 256K x 18 memory configurations
x Supports high system speed:
Commercial and Industrial:
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
x LBO input selects interleaved or linear burst mode
x Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
x 3.3V core power supply
x Power down controlled by ZZ input
x 2.5V I/O
x Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
x Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA)
Pin Description Summary
Description
The IDT71V2576/78 are high-speed SRAMs organized as 128K x
36/256K x 18. The IDT71V2576/78 SRAMs contain write, data, address
and control registers. Internal logic allows the SRAM to generate a self-
timed write based upon a decision which can be left until the end of the write
cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V2576/78 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
datawillbeavailabletotheuseronthenextthreerisingclockedges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V2576/78 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
A0-A17
Address Inputs
Input Synchronous
CE Chip Enable
Input Synchronous
CS0, CS1
Chip Selects
Input Synchronous
OE Output Enable
Input Asynchronous
GW Global Write Enable
Input Synchronous
BWE Byte Write Enable
Input Synchronous
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
Input Synchronous
CLK Clock
Input N/A
ADV Burst Address Advance
Input Synchronous
ADSC
Address Status (Cache Controller)
Input Synchronous
ADSP
Address Status (Processor)
Input Synchronous
LBO Linear / Interleaved Burst Order
Input DC
TMS Test Mode Select
Input Synchronous
TDI Test Data Input
Input Synchronous
TCK Test Clock
Input N/A
TDO Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input Asynchronous
ZZ Sleep Mode
Input Asynchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
N/A
VSS Ground
Supply
N/A
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V2578.
©2003 Integrated Device Technology, Inc.
1
4876 tbl 01
JUNE 2003
DSC-4876/09

1 page




IDT71V2576YSA133PFI pdf
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VDD/NC(1)
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ(2)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
,
4876 drw 02
100 TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.452

5 Page





IDT71V2576YSA133PFI arduino
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1, 2)
Operation GW BWE BW1 BW2 BW3 BW4
Read H H X X X X
Read H L H H H H
Write all Bytes
L
X
X
X
X
X
Write all Bytes
H
L
L
L
L
L
Write Byte 1(3)
H
L
L
H
H
H
Write Byte 2(3)
H
L
H
L
H
H
Write Byte 3(3)
H
L
H
H
L
H
Write Byte 4(3)
H
L
H
H
H
L
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V2578.
3. Multiple bytes may be selected during the same cycle.
4876 tbl 12
Asynchronous Truth Table(1)
Operation(2)
OE
Read L
Read H
Write X
Deselected
X
Sleep Mode
X
ZZ
L
L
L
L
H
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
I/O Status
Data Out
High-Z
High-Z – Data In
High-Z
High-Z
Power
Active
Active
Active
Standby
Sleep
4876 tbl 13
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Add re ss
000 110 11
Se co nd Ad d ress
0 10 0 1 1 10
Third A dd re ss
10 11000 1
Fo urth A d d re s s (1)
1 1 10 0 10 0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
4876 tbl 14
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address
000 110 11
Second Address
0 1 10 1 100
Third Address
10 11000 1
Fourth Address(1)
1100 0 110
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
4876 tbl 15
6.1412

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