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PDF IDT71V124SA15Y Data sheet ( Hoja de datos )

Número de pieza IDT71V124SA15Y
Descripción 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
Ground Pinout
IDT71V124SA
Features
x 128K x 8 advanced high-speed CMOS static RAM
x JEDEC revolutionary pinout (center power/GND) for
reduced noise
x Equal access and cycle times
– Commercial: 10/12/15/20ns
– Industrial: 10/12/15/20ns
x One Chip Select plus one Output Enable pin
x Inputs and outputs are LVTTL-compatible
x Single 3.3V supply
x Low power consumption via chip deselect
x Available in a 32-pin 300- and 400-mil Plastic SOJ, and
32-pin Type II TSOP packages.
Description
The IDT71V124 is a 1,048,576-bit high-speed static RAM organized
as 128K x 8. It is fabricated using IDT’s high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs. The JEDEC center power/GND pinout reduces
noise generation and improves system performance.
The IDT71V124 has an output enable pin which operates as fast as
5ns, with address access times as fast as 9ns available. All bidirec-
tional inputs and outputs of the IDT71V124 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
Functional Block Diagram
A0
A16
ADDRESS
DECODER
1,048,576-BIT
MEMORY ARRAY
I/O0 - I/O7
8
8
WE
OE CONTROL
CS LOGIC
I/O CONTROL
8
.
3873 drw 01
NOVEMBER 2003
©2003- Integrated Device Technology, Inc.
1
DSC-3873/07

1 page




IDT71V124SA15Y pdf
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Timing Waveform of Read Cycle No. 1(1)
ADDRESS
OE
CS
DATAOUT
tRC
tAA
tOE
tOLZ (5)
tCLZ(5)
tACS(3)
HIGH IMPEDANCE
Commercial and Industrial Temperature Ranges
tOHZ (5)
tCHZ(5)
DATAOUT VALID
.
3873 drw 05
Timing Waveform of Read Cycle No. 2(1, 2, 4)
ADDRESS
DATAOUT
tRC
tOH
PREVIOUS DATAOUT VALID
tAA
tOH
DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
.3873 drw 06
6.452

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