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PDF IDT71V016S15PHI Data sheet ( Hoja de datos )
| Número de pieza | IDT71V016S15PHI | |
| Descripción | 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
IDT71V016
Features
Description
◆ 64K x 16 advanced high-speed CMOS Static RAM
The IDT71V016 is a 1,048,576-bit high-speed Static RAM
◆ Commercial (0° to +70°C) and Industrial (–40°C to +85°C) organized as 64K x 16. It is fabricated using IDT’s high-perfomance,
◆ Equal access and cycle times
high-reliability CMOS technology. This state-of-the-art technology,
— Commercial and Industrial: 15/20ns
combined with innovative circuit design techniques, provides a
◆ One Chip Select plus one Output Enable pin
cost-effective solution for high-speed memory needs.
◆ Bidirectional data inputs and outputs directly
The IDT71V016 has an output enable pin which operates as fast
LVTTL-compatible
as 7ns, with address access times as fast as 12ns. All bidirectional
◆ Low power consumption via chip deselect
◆ Upper and Lower Byte Enable Pins
◆ Single 3.3V (±0.3V) power supply
◆ Available in 44-pin Plastic SOJ and 44-pin TSOP
Epackage.
N CFunctional Block Diagram
I N AOutput
T EOE Enable
S SBuffer
inputs and outputs of the IDT71V016 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous circuitry
is used, requiring no clocks or refresh for operation.
The IDT71V016 is packaged in a JEDEC standard 44-pin
Plastic SOJ and 44-pin TSOP Type II.
AR SC 016 IGNA0-A15
Address
Buffers
P LE 71VDESChip
OCS Enable
RBuffer
BS RDE NEWWrite
WE Enable
O OFORBuffer
Row / Column
Decoders
64K x 16
Memory
Array
8
Sense
16 Amps
and
Write
Drivers
8
High
Byte
I/O
Buffer
Low
Byte
I/O
Buffer
I/O15
8
I/O8
I/O7
8
I/O0
BHE
Byte
Enable
Buffers
BLE
©2000 Integrated Device Technology, Inc.
3211 drw 01
AUGUST 2000
1
DSC-3211/08
1 page  
IDT71V016, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = 3.3V ± 0.3V, Commercial and Industrial Temperature Ranges)
71V016S15
71V016S20
Symbol
Parameter
Min. Max. Min. Max.
READ CYCLE
tRC Read Cycle Time
15 ____ 20 ____
tAA Address Access Time
____ 15 ____ 20
tACS Chip Select Access Time
____ 15 ____ 20
tCLZ(1)
Chip Select Low to Output in Low-Z
5 5____ ____
tCHZ(1)
Chip Select High to Output in High-Z
6 8____ ____
tOE Output Enable Low to Output Valid
tOLZ(1)
Output Enable Low to Output in Low-Z
EtOHZ(1)
Output Enable High to Output in High-Z
tOH Output Hold from Address Change
N CtBE Byte Enable Low to Output Valid
I NtBLZ(1)
Byte Enable Low to Output in Low-Z
AtBHZ(1)
Byte Enable High to Output in High-Z
T E S SWRITE CYCLE
R C 16 NtWC Write Cycle Time
A S 0 GtAW Address Valid to End of Write
ItCW Chip Select Low to End of Write
P E V StBW Byte Enable Low to End of Write
L 1 EtAS Address Set-up Time
7 DtWR Address Hold from End of Write
O RtWP Write Pulse Width
S E WtDW Data Valid to End of Write
D EtDH Data Hold Time
B R NtOW(1)
Write Enable High to Output in Low-Z
tWHZ(1)
Write Enable Low to Output in High-Z
____ 8 ____ 10
0 0____ ____
6 8____ ____
4—5—
— 8 ____ 10
0 0____ ____
6 8____ ____
15 ____ 20 ____
10 ____ 12 ____
10 ____ 12 ____
10 ____ 12 ____
0 0____ ____
0 0____ ____
10 ____ 12 ____
8 10____ ____
0 0____ ____
1 ____
1 ____
6 8____ ____
O O RNOTE:
FO1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
Timing Waveform of Read Cycle No. 1(1,2,3)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3211 tbl 10
ADDRESS
DATAOUT
tRC
tOH
PREVIOUS DATAOUT VALID
tAA
tOH
DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
6.452
3211 drw 07
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet IDT71V016S15PHI.PDF ] | |
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