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PDF IDT71T75602S225BG Data sheet ( Hoja de datos )

Número de pieza IDT71T75602S225BG
Descripción 512K x 36/ 1M x 18 2.5V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs
Fabricantes Integrated Device Technology 
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No Preview Available ! IDT71T75602S225BG Hoja de datos, Descripción, Manual

512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
IDT71T75602
IDT71T75802
Features
x 512K x 36, 1M x 18 memory configurations
x Supports high performance system speed - 225 MHz
(3.0 ns Clock-to-Data Access)
x ZBTTM Feature - No dead cycles between write and read
cycles
x Internally synchronized output buffer enable eliminates the
need to control OE
x Single R/W (READ/WRITE) control pin
x Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
x 4-word burst capability (interleaved or linear)
x Individual byte write (BW1 - BW4) control (May tie active)
x Three chip enables for simple depth expansion
x 2.5V power supply (±5%)
x 2.5V I/O Supply (VDDQ)
x Power down controlled by ZZ input
x Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
x Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Description
The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit
(18 Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead
bus cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBTTM, or Zero
Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71T75602/802 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable CEN pin allows operation of the IDT71T75602/802
to be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
Pin Description Summary
A0-A19
Address Inputs
CE1, CE2, CE2
Chip Enables
OE Output Enable
R/W Read/Write Signal
CEN Clock Enable
BW1, BW2, BW3, BW4
Individual Byte Write Selects
CLK Clock
ADV/LD
Advance burst address / Load new address
LBO Linear / Interleaved Burst Order
TMS Test Mode Select
TDI Test Data Input
TCK Test Clock
TDO Test Data Input
TRST
JTAG Reset (Optional)
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS Ground
©2004 Integrated Device Technology, Inc.
1
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
N/A
N/A
N/A
N/A
Asynchronous
Synchronous
Synchronous
Static
Static
5313 tbl 01
APRIL 2004
DSC-5313/08

1 page




IDT71T75602S225BG pdf
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 1Mx 18
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
Industrial
Unit
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VTERM(2)
Terminal Voltage with
Respect to GND
-0.5 to +3.6
-0.5 to +3.6
V
NC
NC
NC
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
VDD(1)
VDD
VDD(1)
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VDD(1)
VDD
ZZ
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
,
5313 drw 02a
Top View
NOTES:
100 TQFP
1. Pins 14, 16, and 66 do not have to be connected directly to VDD as long as
the input voltage is VIH.
2. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To
disable the TAP controller without interfering with normal operation, several
settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and
pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK)
pins 38, 39 and 43 could be left unconnected “NC” and the JTAG circuit
will remain disabled from power up.
3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin
TQFP package for the 36M ZBT device.
VTERM(3,6)
VTERM(4,6)
VTERM(5,6)
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD
V
-0.5 to VDD +0.5 -0.5 to VDD +0.5 V
-0.5 to VDDQ +0.5 -0.5 to VDDQ +0.5 V
TA(7)
Operating Ambient
Temperature
0 to +70
-40 to +85
oC
TBIAS Temperature Under Bias -55 to +125
-55 to +125
oC
TSTG Storage Temperature
-55 to +125
-55 to +125
oC
PT Power Dissipation 2.0 2.0 W
IOUT DC Output Current 50 50 mA
NOTES:
5313 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. During production testing, the case temperature equals TA.
100-Pin TQFP Capacitance
(TA = +25°C, f = 1.0MHz)
165 fBGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions Max. Unit
Symbol
Parameter(1)
Conditions Max. Unit
CIN Input Capacitance
VIN = 3dV
5 pF
CIN Input Capacitance
VIN = 3dV
7 pF
CI/O I/O Capacitance
VOUT = 3dV
7 pF
5313 tbl 07
CI/O I/O Capacitance
VOUT = 3dV
7 pF
5313 tbl 07b
119 BGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions Max. Unit
CIN Input Capacitance
VIN = 3dV
7 pF
CI/O I/O Capacitance
VOUT = 3dV
7 pF
5313 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.452

5 Page





IDT71T75602S225BG arduino
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
Cycle
Address
R/W ADV/LD CE(2) CEN BWx
OE
I/O Comments
n A0 H L L L X X X Address and Control meet setup
n+1 X
X X X H X X X Clock n+1 Ignored
n+2 A1 H L L L X X X Clock Valid
n+3 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus.
n+4 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus.
n+5 A2 H L L L X L Q0 Address A0 Read out (bus trans.)
n+6 A3 H L L L X L Q1 Address A1 Read out (bus trans.)
n+7 A4 H L L L X L Q2 Address A2 Read out (bus trans.)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
5313 tbl 17
Write Operation with Clock Enable Used(1)
Cycle
Address
R/W ADV/LD CE(2) CEN BWx
OE
n A0 L L L L L X
n+1 X
X X X HXX
n+2 A1 L L L L L X
n+3 X
X X X HXX
n+4 X
X X X HXX
n+5 A2
LL
LLLX
n+6 A3
LL
LLLX
n+7 A4
LL
LLLX
I/O Comments
X Address and Control meet setup.
X Clock n+1 Ignored.
X Clock Valid.
X Clock Ignored.
X Clock Ignored.
D0 Write Data D0
D1 Write Data D1
D2 Write Data D2
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
5313 tbl 18
6.1412

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