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PDF IDT71L016L100PHI Data sheet ( Hoja de datos )

Número de pieza IDT71L016L100PHI
Descripción LOW POWER 3V CMOS SRAM 1 MEG (64K x 16-BIT)
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
LOW POWER 3V CMOS SRAM
1 MEG (64K x 16-BIT)
ADVANCE
INFORMATION
IDT71L016
FEATURES:
• 64K x 16 Organization
• Wide Operating Voltage Range: 2.7V to 3.6V
• Speed Grades: 70ns, 100ns
• Low Operating Power: 45mA (max)
• Low Standby Power: 5µA (max)
• Low-Voltage Data Retention: 1.5V (min)
• Available in a 44-pin TSOP package
DESCRIPTION:
The IDT71L016 is a 1,048,576-bit very low-power Static
RAM organized as 64K x 16. It is fabricated using IDT’s high-
reliability CMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides
a cost-effective solution for low-power memory needs. It uses
a 6-transistor memory cell.
All input and output signals of the IDT71L016 are LVTTL-
compatible and operation is from a single extended-range
3.3V supply. This extended supply range makes the device
ideally suited for unregulated battery-powered applications.
Fully static asynchronous circuitry is used, requiring no clocks
or refresh for operation.
The IDT71L016 is packaged in a JEDEC standard 44-pin
TSOP Type II.
FUNCTIONAL BLOCK DIAGRAM
Output
OE Enable
Buffer
A0 - A15
Address
Buffers
Chip
CS Enable
Buffer
Write
WE Enable
Buffer
Row / Column
Decoders
64K x 16
Memory
Array
8
Sense
16 Amps
and
Write
Drivers
8
High
Byte
I/O
Buffer
Low
Byte
I/O
Buffer
I/O 15
8
I/O 8
I/O 7
8
I/O 0
BHE
BLE
Byte
Enable
Buffers
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
©1997 Integrated Device Technology, Inc.
3771 drw 01
MAY 1997
DSC-3771/2
1

1 page




IDT71L016L100PHI pdf
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VDD = 2.7 to 3.6V, All Temperature Ranges)
71L016L70
Symbol
Read Cycle
tRC
Parameter
Read Cycle Time
Min. Max.
70 —
tAA Address Access Time
— 70
tACS
tCLZ(1)
tCHZ(1)
Chip Select Access Time
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
— 70
10 —
— 25
tOE
tOLZ(1)
tOHZ(1)
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
— 35
5—
— 25
tOH Output Hold from Address Change
10 —
tBE
tBLZ(1)
tBHZ(1)
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
— 35
5—
— 25
Write Cycle
tWC Write Cycle Time
70 —
tAW Address Valid to End of Write
65 —
tCW Chip Select Low to End of Write
65 —
tBW Byte Enable Low to End of Write
65 —
tAS Address Set-up Time
0—
tWR Address Hold from End of Write
0—
tWP Write Pulse Width
55 —
tDW Data Valid to End of Write
30 —
tDH
tOW(1)
tWHZ(1)
Data Hold Time
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
0—
5—
— 25
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
71L016L100
Min. Max. Units
100 — ns
— 100 ns
— 100 ns
10 — ns
— 30 ns
— 50 ns
5 — ns
— 30 ns
15 — ns
— 50 ns
5 — ns
— 30 ns
100 — ns
80 — ns
80 — ns
80 — ns
0 — ns
0 — ns
70 — ns
40 — ns
0 — ns
5 — ns
— 30 ns
3771 tbl 10
TIMING WAVEFORM OF READ CYCLE NO. 1(1,2,3)
ADDRESS
DATAOUT
tRC
tAA
tOH
PREVIOUS DATAOUT VALID
tOH
DATAOUT VALID
3771 drw 06
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
5

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