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PDF IDT71F432 Data sheet ( Hoja de datos )

Número de pieza IDT71F432
Descripción 32k X 32 mcACHE synchronous pipelined cache ram
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
32K x 32 MCache
SYNCHRONOUS PIPELINED
CACHE RAM
IDT71F432
FEATURES:
• Uses IDT's Fusion Memory technology
• 66 and 75 MHz speed grades
• 3-1-1-1 Pipelined Burst Read
• 3-1-1-1 Pipelined Burst Write
• 3-1-1-1-1-1-1-1... extended pipelined operation
• Refresh overhead consumes less than 0.5% of cycles
• Pinout is superset of industry standard PBSRAM
• Interchangeable with PBSRAM in new designs
• Compatible with MoSys MCache™ devices
• Low operating and standby power consumption
1/3 the power of standard PBSRAM
• Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP)
DESCRIPTION:
The IDT71F432 MCache is a high-performance, low-power
replacement for standard 32K x 32 pipelined burst SRAM
(PBSRAM) in cache applications. The 71F432 is built using
IDT's Fusion Memory technology, which combines the perfor-
mance of SRAM with the cost structure of DRAM. It is
fundamentally compatible with standard PBSRAM, with addi-
tional features to accommodate the internal DRAM operation
of the memory. These additional features are defined so that
71F432 compatible system controllers and properly imple-
mented PC boards can work transparently with either the
71F432 or PBSRAM in cache memory applications.
Six pins, identified as No Connect (NC) on the standard
PBSRAM specifications, are used to support 71F432 opera-
tion. These pins are 5V supply (2), host bus W/R#, RESET#
and two proprietary functions labeled F0 and F1. When using
standard PBSRAM, these pins have no effect and the associ-
ated functions in the 71F432-compatible chipset are not
activated.
The 71F432 supports PBSRAM operating modes, includ-
ing burst read (3-1-1-1), burst write (3-1-1-1) and pipelined
burst read or write (3-1-1-1-1-1...). As with all DRAM devices,
refresh is required. The memory is not accessible during the
refresh interval. Refresh occupies 0.5% of the clock cycles,
resulting in a system performance reduction of less than 0.1%.
ABOUT IDT'S Fusion Memory TECHNOLOGY:
What is Fusion Memory?
• Fusion Memory is a new kind of memory technology that
combines the high performance and ease-of-use of SRAM
with the manufacturing costs of DRAM.
Why are Fusion Memory chips so much smaller than SRAM?
• Traditional SRAM uses four or six transistors to make each
memory cell. Fusion Memory uses only one transistor for
each memory cell, so the memory array itself is only about
1/4 the size of an SRAM.
Is Fusion Memory the same as Dynamic Memory?
• Not exactly. While both Fusion Memory and DRAMs use
single-transistor dynamic cells for storage, Fusion Memo-
ries use much different designs for all the surrounding
circuitry, such as address drivers, sense amps, and control
circuitry. This gives Fusion Memory a performance level
that is much higher than DRAM.
How does the performance of Fusion Memory cache RAMs
compare with synchronous burst SRAMS?
• The Fusion Memory devices equal the performance of the
SRAMs they are designed to replace.
Are Fusion Memory and PBSRAMs interchangeable?
• A system designed to use the Fusion Memory cache RAMs
can use standard PBSRAMs instead.
What is the difference between MoSys MCache™ and IDT’s
Fusion Memory?
• MCache is MoSys’ trademark for their cache memory
devices. Fusion Memory is IDT’s trademark for the under-
lying technology. IDT will use the technology in other
products besides cache RAMs. The IDT71F432 and
MoSys' MCache devices are interchangeable.
Fusion
Memory
SRAM
If Fusion Memory uses dynamic storage, are there refresh
cycles?
• Yes, but the refresh control is handled automatically and
nearly invisibly, using either on-chip circuitry or circuitry in
the chip set used with the memory device. The perfor-
mance penalty is typically less than 0.1%.
DRAM
Cost
Fusion Memory™ Provides SRAM Performance at DRAM Cost
The IDT logo is a registered trademark and Fusion Memory and CacheRAM are trademarks of Integrated Device Technology
Pentium is a trademark of Intel Corp.
MCache is a trademark of MoSys, Inc.
COMMERCIAL TEMPERATURE RANGE
DECEMBER 1996
©1996 Integrated Device Technology, Inc.
13.1
DSC-3555/3
1

1 page




IDT71F432 pdf
IDT71F432 32Kx32 MCache SYNCHRONOUS PIPELINED CACHE RAM
PIN CONFIGURATION
COMMERCIAL TEMPERATURE RANGE
NC
I/O16
I/O17
VDD
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDD
I/O22
I/O23
NC
VDD
VDD5
VSS
I/O24
I/O25
VDD
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDD
I/O30
I/O31
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 PK100-1 66
16 65
17 64
18
14mm x 20mm x 1.4mm body
63
19
1.6mm max total height
62
20
21
0.65mm pin pitch
61
60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
I/O15
I/O14
VDD
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDD
I/O9
I/O8
VSS
VDD5
VDD
NC
I/O7
I/O6
VDD
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDD
I/O1
I/O0
NC
TOP VIEW
TQFP
ORDERING INFORMATION
IDT 71F432
Device
Type
X
Power
XX
Speed
PF
Package
75
66
Speed in MHz
S Standard Power (66 and 75 MHz)
L Low Power (66 MHz only)
13.1 5

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