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PDF IDT7198S85DB Data sheet ( Hoja de datos )

Número de pieza IDT7198S85DB
Descripción CMOS STATIC RAMs 64K (16K x 4-BIT) Added Chip Select and Output Controls
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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®
Integrated Device Technology, Inc.
CMOS STATIC RAMs
64K (16K x 4-BIT)
Added Chip Select and Output Controls
IDT7198S
IDT7198L
FEATURES:
• Fast Output Enable (OE) pin available for added system
flexibility
• Multiple Chip Selects (CS1, CS2) simplify system design
and operation
• High speed (equal access and cycle times)
— Military: 20/25/35/45/55/70/85ns (max.)
• Low power consumption
• Battery back-up operation—2V data retention (L version
only)
• 24-pin CERDIP, high-density 28-pin leadless chip carrier,
and 24-pin CERPACK packaging available
• Produced with advanced CMOS technology
• Bidirectional data inputs and outputs
• Inputs/outputs TTL-compatible
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT7198 is a 65,536 bit high-speed static RAM orga-
nized as 16K x 4. It is fabricated using IDT’s high-perfor-
mance, high-reliability technology—CMOS. This state-of-the-
art technology, combined with innovative circuit design tech-
niques, provides a cost effective approach for memory inten-
sive applications.
Access times as fast as 20ns are available. The IDT7198
offers a reduced power standby mode, ISB1, which is activated
when CS1 or CS2 goes HIGH. This capability decreases
power, while enhancing system reliability. The low-power
version (L) also offers a battery backup data retention capa-
bility where the circuit typically consumes only 30µW when
operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate
from a single 5V supply.
The lDT7198 is packaged in either a 24-pin ceramic DlP,
28-pin leadless chip carrier, and 24-pin CERPACK.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0
DECODER
65,536-BIT
MEMORY ARRAY
VCC
GND
A13
I/O0
I/O1
I/O2
I/O3
INPUT
DATA
CONTROL
COLUMN I/O
CS1
CS2
WE1
OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY TEMPERATURE RANGE
©1994 Integrated Device Technology, Inc.
6.4
2985 drw 01
MAY 1994
DSC-1027/4
1

1 page




IDT7198S85DB pdf
IDT7198S/L
CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, Military Temperature Range)
7198S20
7198L20
7198S25 7198S35/45 7198S55
7198L25 7198L35/45 7198L55
7198S70
7198L70
7198S85
7198L85
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time
20 — 25 — 35/45 — 55 — 70 — 85 — ns
tAA Address Access Time
tACS1,2(1) Chip Select-1,2 Access Time
tCLZ1,2(2) Chip Select-1,2 to Output in Low-Z
— 19 — 25 — 35/45 — 55 — 70 — 85 ns
— 20 — 25 — 35/45 — 55 — 70 — 85 ns
5 — 5 — 5 — 5 — 5 — 5 — ns
tOE Output Enable to Output Valid
tOLZ(2) Output Enable to Output in Low-Z
tCHZ1,2(2) Chip Select 1,2 to Output in High-Z
tOHZ(2) Output Disable to Output in High-Z
— 9 — 11 — 20/25 — 35 — 45 — 55 ns
5 — 5 — 5 — 5 — 5 — 5 — ns
— 8 — 10 — 14 — 20 — 25 — 30 ns
— 8 — 9 — 15 — 20 — 25 — 30 ns
tOH Output Hold from Address Change 5 — 5 — 5 — 5 — 5 — 5 — ns
tPU(2) Chip Select to Power Up Time
0 — 0 — 0 — 0 — 0 — 0 — ns
tPD(2) Chip Deselect to Power Down Time — 20 — 25 — 35/45 — 55 — 70 — 85 ns
NOTES:
1. Both chip selects must be active low for the device to be selected.
2. This parameter is guaranteed by device characterization but is not production tested.
2985 tbl 11
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS
tRC
tAA
OE
CS1, 2
DATAOUT
tOE
tOLZ (5)
tACS1, 2
tCLZ1, 2 (5)
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS1 is LOW, CS2 is LOW.
3. Address valid prior to or coincident with CS1 and or CS2 transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state voltage.
tOH
tOHZ(5)
tCHZ1, 2 (5)
DATA VALID
2985 drw 07
6.4 5

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