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PDF IDT7188S Data sheet ( Hoja de datos )

Número de pieza IDT7188S
Descripción CMOS STATIC RAM 64K 16K x 4-BIT
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
CMOS STATIC RAM
64K (16K x 4-BIT)
IDT7188S
IDT7188L
FEATURES:
• High-speed (equal access and cycle times)
— Military: 25/35/45/55/70/85ns (max.)
• Low power consumption
• Battery backup operation — 2V data retention (L version
only)
• Available in high-density industry standard 22-pin, 300
mil ceramic DIP
• Produced with advanced CMOS technology
• Inputs/outputs TTL-compatible
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT7188 is a 65,536-bit high-speed static RAM
organized as 16K x 4. It is fabricated using IDT’s high-
performance, high-reliability technology — CMOS. This state-
of-the-art technology, combined with innovative circuit design
techniques, provides a cost effective approach for memory
intensive applications.
Access times as fast as 25ns are available. The IDT7188
offers a reduced power standby mode, ISB1, which is activated
when CS goes HIGH. This capability significantly decreases
power while enhancing system reliability. The low-power
version (L) version also offers a battery backup data retention
capability where the circuit typically consumes only 30µW
operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate
from a single 5V supply. The IDT7188 is packaged in 22-pin,
300 mil ceramic DIP providing excellent board-level packing
densities.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0
DECODER
65,536-BIT
MEMORY ARRAY
VCC
GND
A13
I/O0
I/O1
I/O2
I/O3
INPUT
DATA
CONTROL
COLUMN I/O
CS
WE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
6.3
2989 drw 01
AUGUST 1996
DSC-2989/7
1

1 page




IDT7188S pdf
IDT7188S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
Symbol
Parameter
7188S25
7188L25
7188S35/45 7188S55/70
7188L35/45 7188L55/70
7188S85
7188L85
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time
25 — 35/45 — 55/70 — 85 — ns
tAA Address Access Time
— 25 — 35/45 — 55/70 — 85 ns
tACS Chip Select Access Time
— 25 — 35/45 — 55/70 — 85 ns
tOH Output Hold from Address Change
5 — 5 — 5 — 5 — ns
tLZ(1) Output Selection to Output in Low-Z
5 — 5 — 5 — 5 — ns
tHZ(1) Chip Deselect to Output in High-Z
— 10 — 14 — 20/25 — 30 ns
tPU(1) Chip Select to Power Up Time
0 — 0 — 0 — 0 — ns
tPD(1) Chip Deselect to Power Down Time
— 25 — 35/45 — 55/70 — 85 ns
NOTES:
1. This parameter is guaranteed by device characterization but is not production tested.
2989 tbl 11
TIMING WAVEFORM OF READ CYCLE NO. 1(1, 2)
tRC (5)
ADDRESS
DATAOUT
tAA
tOH
PREVIOUS DATA VALID
DATA VALID
2989 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 3)
tRC (5)
CS
DATAOUT
VCC SUPPLY ICC
CURRENT ISB
tACS
tLZ (4)
tPU
tHZ (4)
DATA VALID
tPD
NOTES:
1. WE is HIGH for Read cycle.
2. CS is LOW for Read cycle.
3. Address valid prior to or coincident with CS transition LOW.
4. Transition is measured ±200mV from steady state voltage.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
HIGH IMPEDANCE
2989 drw 07
6.3 5

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