|
|
PDF INDEX61075MHZ Data sheet ( Hoja de datos )
| Número de pieza | INDEX61075MHZ | |
| Descripción | PENTIUM PROCESSOR at iCOMP INDEX 61075 MHz | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de INDEX61075MHZ (archivo pdf) en la parte inferior de esta página. Total 48 Páginas | ||
|
No Preview Available !
E
PENTIUM® PROCESSOR at iCOMP® INDEX 610\75 MHz
n Compatible with Large Software Base
− MS-DOS*, Windows*, OS/2*, UNIX*
n 32-Bit CPU with 64-Bit Data Bus
n Superscalar Architecture
− Two Pipelined Integer Units Are
Capable of 2 Instructions/Clock
− Pipelined Floating Point Unit
n Separate Code and Data Caches
− 8K Code, 8K Writeback Data
− MESI Cache Protocol
n Advanced Design Features
− Branch Prediction
− Virtual Mode Extensions
n 3.3V BiCMOS Silicon Technology
n 4M Pages for Increased TLB Hit Rate
n IEEE 1149.1 Boundary Scan
n Internal Error Detection Features
n SL Enhanced Power Management
Features
− System Management Mode
− Clock Control
n Fractional Bus Operation
− 75-MHz Core / 50-MHz Bus
The Pentium® processor is fully compatible with the entire installed base of applications for DOS*, Windows*,
OS/2*, and UNIX*, and all other software that runs on any earlier Intel 8086 family product. The Pentium
processor’s superscalar architecture can execute two instructions per clock cycle. Branch prediction and
separate caches also increase performance. The pipelined floating-point unit delivers workstation level
performance. Separate code and data caches reduce cache conflicts while remaining software transparent. The
Pentium processor (610\75) has 3.3 million transistors, is built on Intel’s advanced 3.3V BiCMOS silicon
technology, and has full SL Enhanced power management features, including System Management Mode
(SMM) and clock control. The additional SL Enhanced features, 3.3V operation, and the TCP package, which
are not available in the Pentium processor (510\60, 567\66), make the Pentium processor (610\75) TCP ideal for
enabling mobile Pentium processor designs. The Pentium processor may contain design defects or errors
known as errata which may cause the product to deviate from published specifications. Current characterized
errata are available upon request.
June 1997
Order Number 242323-004
1 page  
PENTIUM® PROCESSOR (610\75)
• Virtual Mode Extensions
2.1. Pentium® Processor Family
Architecture
The application instruction set of the Pentium
processor family includes the complete Intel486
CPU family instruction set with extensions to
accommodate some of the additional functionality
of the Pentium processors. All application software
written for the Intel386 and Intel486 family
microprocessors will run on the Pentium processors
without modification. The on-chip memory
management unit (MMU) is completely compatible
with the Intel386 family and Intel486 family of
CPUs.
The Pentium processors implement several
enhancements to increase performance. The two
instruction pipelines and floating-point unit on
Pentium processors are capable of independent
operation. Each pipeline issues frequently used
instructions in a single clock. Together, the dual
pipes can issue two integer instructions in one
clock, or one floating point instruction (under certain
circumstances, two floating-point instructions) in
one clock.
Branch prediction is implemented in the Pentium
processors. To support this, Pentium processors
implement two prefetch buffers, one to prefetch
code in a linear fashion, and one that prefetches
code according to the BTB so the needed code is
almost always prefetched before it is needed for
execution.
The floating-point unit has been completely
redesigned over the Intel486 CPU. Faster
algorithms provide up to 10X speed-up for common
operations including add, multiply, and load.
Pentium processors include separate code and
data caches integrated on-chip to meet perform-
ance goals. Each cache is 8 Kbytes in size, with a
32-byte line size and is 2-way set associative. Each
cache has a dedicated Translation Lookaside Buffer
(TLB) to translate linear addresses to physical
addresses. The data cache is configurable to be
writeback or writethrough on a line-by-line basis
and follows the MESI protocol. The data cache tags
are triple ported to support two data transfers and
an inquire cycle in the same clock. The code cache
is an inherently write-protected cache. The code
cache tags are also triple ported to support
snooping and split line accesses. Individual pages
can be configured as cacheable or non-cacheable
by software or hardware. The caches can be
enabled or disabled by software or hardware.
The Pentium processors have increased the data
bus to 64 bits to improve the data transfer rate.
Burst read and burst writeback cycles are
supported by the Pentium processors. In addition,
bus cycle pipelining has been added to allow two
bus cycles to be in progress simultaneously. The
Pentium processors' Memory Management Unit
contains optional extensions to the architecture
which allow 2-Mbyte and 4-Mbyte page sizes.
The Pentium processors have added significant
data integrity and error detection capability. Data
parity checking is still supported on a byte-by-byte
basis. Address parity checking, and internal parity
checking features have been added along with a
new exception, the ma chine check exception.
As more and more functions are integrated on chip,
the complexity of board level testing is increased.
To address this, the Pentium processors have
increased test and debug capability. The Pentium
processors implement IEEE Boundary Scan
(Standard 1149.1). In addition, the Pentium
processors have specified 4 breakpoint pins that
correspond to each of the debug registers and
externally indicate a breakpoint match. Execution
tracing provides external indications when an
instruction has completed execution in either of the
two internal pipelines, or when a branch has been
taken.
System Management Mode (SMM) has been
implemented along with some extensions to the
SMM architecture. Enhancements to the virtual
8086 mode have been made to increase
performance by reducing the number of times it is
necessary to trap to a vir tual 8086 monitor.
3
5 Page 
PENTIUM® PROCESSOR (610\75)
Table 2. TCP Pin Cross Reference by Pin Name (Contd.)
Vcc
1*
35
73
123
168*
190*
230
257*
295
2
41* 79
129
170*
195*
232*
258
301
6*
43
85
135
172*
204
236
260*
304*
11* 49* 91
141
174*
210
240*
264
306
17* 51
97
147
177*
216
241
266*
309*
19
57*
103
153*
178
217*
243*
268*
313
23
59
109
157*
180*
221
247
275
317*
27*
65*
111*
160
183*
225*
249*
281
33* 67
117
165*
188*
226
253
291
Vss
3 50 104 166 209 250 302
7 52 110 169 215 252 305
12 58 112 171 218 256 307
18 60 118 173 220 261 310
20 66 124 176 224 263 314
24 68 130 179 229 267 320
26 74 136 182 233 269
32 80 142 187 235 274
36 86 148 189 239 280
42 92 154 194 244 290
44 98 159 203 246 294
NC
175 184 185 271
NOTE:
*These Vcc pins are 3.3V supplies for the Pentium processor (610\75) TCP but will be lower voltage pins on future offerings of
this microprocessor family. All other V cc pins will remain at 3.3V.
3.2. Design Notes
For reliable operation, always connect unused
inputs to an appropriate signal level. Unused active
low inputs should be connected to Vcc. Unused
active HIGH inputs should be connected to GND
(Vss).
No Connect (NC) pins must remain unconnected.
Connection of NC pins may result in component
failure or incompatibility with processor steppings.
3.3. Quick Pin Reference
This section gives a brief functional description of
each of the pins. For a detailed description, see the
"Hardware Interface" chapter in the Pentium®
Processor Family Developer’s Manual , Volume 1.
9
11 Page | ||
| Páginas | Total 48 Páginas | |
| PDF Descargar | [ Datasheet INDEX61075MHZ.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| INDEX61075MHZ | PENTIUM PROCESSOR at iCOMP INDEX 61075 MHz | Intel Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |