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PDF IMP706JCPA Data sheet ( Hoja de datos )

Número de pieza IMP706JCPA
Descripción 3/3.3/4.0V P SUPERVISOR CIRCUITS
Fabricantes IMP Inc 
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No Preview Available ! IMP706JCPA Hoja de datos, Descripción, Manual

IMP706P/R/S/T/J, IMP708R/S/T/J
POWER MANAGEMENT
3/3.3/4.0V µP Supervisor Circuits
– Low supply current
– Watchdog timer
– Brownout detection
The IMP706P/R/S/T/J and IMP708R/S/T/J CMOS supervisor circuits
monitor power-supply and battery voltage level, and µP/µC operation.
A reset is generated when the supply drops below 2.63V (IMP706P/R,
IMP708R), 2.93V (IMP706S, IMP708S), 3.08V (IMP706T, IMP708T) or 4.00
(IMP706J, IMP708J).
The family offers several functional options. Each device generates a
reset signal during power-up, power-down and during brownout
conditions.
In addition, the IMP706P/R/S/T/J feature a 1.6 second watchdog timer.
The watchdog timer output will trigger a reset if connected to MR.
Unlike competitive devices, floating the WDI input pin disables the
watchdog timer.
The IMP708R/S/T/J have both active-HIGH and active-LOW reset out-
puts but no watchdog function. The IMP706P has the same pin-out and
functions as the IMP706R but has an active-HIGH reset output.
A versatile power-fail circuit, useful in checking battery levels and
non-5V supplies, has a 1.25V threshold. All devices have a manual
reset input.
All devices are available in 8-pin DIP, SO and the compact MicroSO
packages. The MicroSO package requires 50% less PC board area than
the conventional SO package.
Block Diagrams
Key Features
N Lower power, pin compatible replacements for
Maxim MAX706P/R/S/T, MAX708R/S/T
– 30% lower supply current:140µA vs. 200µA
N Precision power supply monitor
– 2.63V threshold (IMP706P/R, IMP708R)
– 2.93V threshold (IMP706S, IMP708S)
– 3.08V threshold (IMP706T, IMP708T)
– New 4.00V threshold (IMP706J, IMP708J)
N Debounced manual reset input
N Auxiliary voltage monitor comparator
– 1.25V threshold
– Battery monitor/auxiliary supply monitor
N Watchdog timer (IMP706P/R/S/T/J)
– Watchdog can be disabled by floating WDI
N 200ms reset time delay
N Three reset signal options
– Active HIGH: IMP706P
– Active LOW: IMP706R/S/T/J
– Active HIGH & LOW outputs: IMP708R/S/T/J
N DIP, SO and MicroSO packages
N Guaranteed RESET assertion to VCC = 1.1V
Applications
N Computers and controllers
N CTI applications
N Embedded controllers
N Battery operated systems
N Intelligent instruments
N Wireless communication systems
N PDAs and handheld equipment
WDI
MR
VCC
PFI
Transition
Detector
VCC
20k
Watchdog
Timer
Timebase
RESET
Generator
+
+
2.63V (IMP706P/R)
2.93V (IMP706S)
3.08V (IMP706T)
4.00V (IMP706J)
+
1.25V
IMP706P/R/S/T/J
© 1999 IMP, Inc.
GND
WDO
RESET
(RESET) IMP706P
PFO
MR
VCC
PFI
VCC
20k
RESET
Generator
+
+–
2.63V (IMP708R)
2.93V (IMP708S)
3.08V (IMP708T)
4.00V (IMP708J)
+
1.25V
RESET
RESET
PFO
IMP708R/S/T/J
706P_01.eps
GND
706P_02.eps
408-432-9100/www.impweb.com
1

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IMP706JCPA pdf
IMP706P/R/S/T/J, IMP708R/S/T/J
Pin Descriptions
Pin Number
IMP706P
IMP706R/S/T/J IMP708R/S/T/J
DIP/SO MicroSO DIP/SO MicroSO DIP/SO MicroSO Name
1 3 1 3 1 3 MR
2 4 2 4 2 4 VCC
3 5 3 5 3 5 GND
4 6 4 6 4 6 PFI
5 7 5 7 5 7 PFO
6 8 6 8 — — WDI
— — — — 6 8 NC
——
7
1
7 1 RESET
8 2 8 2 — — WDO
7 1 — — 8 2 RESET
Function
Manual reset input. The active LOW input triggers
a reset pulse. It is pulled HIGH by a 20kpull-up
resistor. It is compatible with TTL/CMOS signals
when VCC = 5V. It can be shorted to ground
through a mechanical switch. Leave floating or
connect to VCC if the function is not used.
Monitored power supply input.
Ground
Power-fail input voltage monitor. With PFI less than
1.25V, PFO goes LOW. Connect PFI to ground
when not used.
Power-fail output. The output is active LOW and
sinks current when PFI is less than 1.25V. If not
used, leave the pin unconnected.
Watchdog input. WDI controls the internal watchdog
timer. A HIGH or LOW signal for 1.6 sec at WDI
allows the internal timer to run-out, setting WDO low.
A rising or falling edge must occur at WDI within
1.6 seconds or WDO goes LOW. The watchdog
function is disabled by floating WDI. The internal
watchdog timer clears when: RESET is asserted;
WDI is three-stated; or WDI sees a rising or falling edge.
Not connected.
Active-LOW reset output. Pulses LOW for 200ms
when triggered, and stays LOW whenever VCC is
below the reset threshold. RESET remains LOW for
200ms after VCC rises above the RESET threshold
or MR goes from HIGH to LOW. A watchdog timeout
will not trigger RESET unless WDO is connected to MR.
Watchdog output. WDO goes LOW when the 1.6
second internal watchdog timer times-out and does
not go HIGH until a transition occurs at WDI. In
addition, when VCC falls below the reset threshold,
WDO goes LOW. Unlike RESET, WDO does not have
a minimum pulse width and as soon as VCC exceeds
the reset threshold, WDO becomes HIGH with no delay.
Active-HIGH reset output. RESET is the inverse of
RESET.
Feature Summary
IMP706P IMP706R IMP706S IMP706T IMP706J IMP708R IMP708S IMP708T IMP708J
Power-fail detector
II
II
II
II
I
Brownout detection
II
II
II
II
I
Debounced manual RESET input I
I
II
II
II
I
Power-up/down RESET
II
II
II
II
I
Watchdog timer
IIII I
Active-HIGH RESET
I
Active-LOW RESET
III I
Active-LOW and HIGH RESETs
I II I
RESET threshold
2.63V 2.63V 2.93V 3.08V 4.00V 2.63V 2.93V 3.08V 4.00V
© 1999 IMP, Inc.
408-432-9100/www.impweb.com
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