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PDF IMP1832S Data sheet ( Hoja de datos )

Número de pieza IMP1832S
Descripción 3.3V P Power Suppl Monitor and Reset Circuit
Fabricantes IMP Inc 
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IMP1832
POWER MANAGEMENT
3.3V µP Power Supply
Monitor and Reset Circuit
– Selectable Trip-Point Tolerance and
Watchdog Period
– Push-Button Reset
– Push-Pull Reset Outputs
The IMP1832 microprocessor supervisor can halt and restart a “hung-
up” or “stalled” microprocessor, restart a microprocessor after a power
failure, and debounce a manual push-button microprocessor reset
switch. The IMP1832 features over 40% lower supply current than the
pin compatible Dallas Semiconductor DS1832.
Precision temperature compensated reference and comparator circuits
monitor the 3.3V, VCC input voltage. During power-up or when the VCC
power supply falls outside selectable tolerance limits, both RESET and
RESET become active. When VCC rises above the threshold voltage, the
reset signals remain active for an additional 250ms minimum, allowing
the power supply and system microprocessor to stabilize. The trip point
tolerance signal, TOL, selects the trip level tolerance to be either 10- or
20-percent.
RESET and RESET outputs are push-pull.
A debounced manual reset input, PBRST, activates the reset outputs for
a minimum period of 250ms.
Key Features
x Pin compatible with the Dallas Semiconductor
DS1832
— Over 40% lower supply current
x 3.3V supply monitor
x Push-pull output
x Selectable watchdog period
x Debounce manual push-button reset input
x Precision temperature-compensated voltage
reference and comparator
x Power-up, power-down and brownout detection
x 250ms minimum reset time
x Active LOW and HIGH reset signal
x Selectable trip point tolerance: 10% or 20%
x Low-cost 8-pin DIP/SO and 8-pin MicroSO
packages
x Wide operating temperature – 40°C to +85°C
Also included is a watchdog timer to stop and restart a
microprocessor that is “hung-up”. Three watchdog time-
out periods are selectable: 150ms, 610ms and 1,200ms. If the
ST input is not strobed LOW before the time-out period
expires, a reset is issued.
Devices are available in 8-pin DIP, 8-pin SO and compact
8-pin MicroSO packages.
Block Diagram
VCC
TOL
PBRST
TD
ST
8 IMP1832
3 10%/20% Tolerance
Selection
Reference
VCC
40k9
1 Push Button
Debounce
2 Watchdog
Timebase Selection
7 Watchdog
Transition Detector
+
Reset &
Watchdog Timer
© 1999 IMP, Inc.
408-432-9100/www.impweb.com
VCC
6
RESET
VCC
5
RESET
4
GND
1832_02.eps
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IMP1832S pdf
IMP1832
Application Information
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that is
“hung-up”. Through the time delay input, TD, three watchdog
time-out periods are selectable: 150ms, 610ms and 1,200ms. If the
strobe input, ST, is not strobed LOW prior to timeout, reset signals
become active. On power-up or after the supply voltage returns to
an in-tolerance condition, the reset signal remains active for
250ms minimum, allowing the power supply and system micro-
processor to stabilize.
ST Pulses as short as 20ns can be detected.
Valid
Valid
Invalid
Strobe
Strobe
Strobe
ST
RESET
tRST
tST
tTD
(Min)
tTD
(Max)
A HIGH-to-LOW ST signal transition must be regularly issued
no later than the minimum time-out period defined by the state of
the TD signal. This guarantees the watchdog timer does not
time-out.
Timeouts periods of approximately 150ms, 610ms or 1,200ms are
selected through the TD pin.
TD Voltage Level
Watchdog Time-Out Period (ms)
Min Nominal Max
GND
62.5 150 250
Floating
250 610 1000
VCC
500
1200
2000
1832_t03.eps
The watchdog timer can not be disabled. It must be strobed with
a high-to-low transition to avoid a watchdog timeout and reset.
Note: ST is ignored whenever a reset is active.
1832_08.eps
Figure 5. Timing Diagram: Strobe Input
Supply
Voltage
IMP1832
1
PBRST
2
TD
8
VCC
7
ST
36
TOL RESET
45
GND RESET
mP
RESET
MREQ
Address
Bus
Figure 6. Application Circuit: Watchdog Timer
Decoder
1832_06.eps
© 1999 IMP, Inc.
408-432-9100/www.impweb.com
5

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