|
|
PDF IMP16C554 Data sheet ( Hoja de datos )
| Número de pieza | IMP16C554 | |
| Descripción | Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFOs | |
| Fabricantes | IMP Inc | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IMP16C554 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
IMP16C554
Data Communications
Quad Universal Asynchronous
Receiver/Transmitter (UART)
with FIFO's
Description
The IMP16C554 is a universal asynchronous receiver and
transmitter with 16 byte transmit and receive FIFO. A
programmable baud rate generator is provided to select
transmit and receive clock rates from 50Hz to 1.5MHz.
The IMP16C554 is an improved version of the IMP16C550
UART with higher operating speed and lower access time.
The IMP16C554 on board status registers provides the
error conditions, type and status of the transfer operation
being performed. Included is complete MODEM control
capability, and a processor interrupt system that may be
software tailored to the user’s requirements. The
IMP16C554 provides internal loop-back capability for on
board diagnostic testing.
The IMP16C554 is fabricated in an advanced 1.2u CMOS
process to achieve low drain power and high speed
requirements.
Pin Configuration
Key Features
16 byte receive FIFO with error flags
Modem control signal (CTS*, RTS*, DSR*, DTR*,
RI* ,CD*)
Programmable character lengths(5,6,7,8)
Even, odd, or no parity bit generation and detection
Status report register
Independent transmit and receive control
TLL compatible inputs. outputs
Software compatible with Ei8250, 1Ei16C550
460.8kHz transmit/receive operation with 7.372
MHz crystal or external clock source
DSRA•
CTSA•
DTRA•
VCC
RTSA•
INTA
CSA•
TXA
IOW•
TXB
CSB•
INTB
RTSB•
GND
DTRB
CTSD•
DSRB•
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
IMP 16C554
60 DSRD•
59 CTSD•
58 DTRD•
57 GND
56 RTSD•
55 INTD
54 CSD•
53 TXD
52 IOR•
51 TXC
50 CSC•
49 INTC
48 RTSC•
47 VCC
46 DTRC•
45 CTSC•
44 DSRC•
68-PIN PLCC
DSRA•
CTSA•
DTRA•
VCC
RTSA•
INTA
CSA•
TXA
IOW•
TXB
CSB•
INTB
RTSB•
GND
DTRB
CTSD•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IMP 16C554
48 DSRD•
47 CTSD•
46 DTRD•
45 GND
44 RTSD•
43 INTD
42 CSD•
41 TXD
40 IOR•
39 TXC
38 CSC•
37 INTC
36 RTSC•
35 VCC
34 DTRC•
33 CTSC•
64-PIN QFP
1
408-432-9100/www.impweb.com
© 2002 IMP, Inc.
1 page  
IMP16C554
IMP16C554 ACCESSIBLE REGISTERS
A2A1A0
000
Registe BIT-7 BIT-6 BIT-5 BIT-4 BIT-3
r
RHR bit-7 bit-6 bit-5 bit-4 bit-3
BIT-2
bit-2
BIT-1
bit-1
BIT-0
bit-0
0 0 0 THR
0 0 1 IER
0 1 0 FCR
0 1 0 ISR
0 1 1 LCR
100
101
MCR
LSR
110
111
000
001
MSR
SPR
DLL
DLM
bit-7
0
RCV
R
trigge
r
(MSB
)
0/FIF
Os
enabl
ed
Divis
or
latch
enabl
e
0
o/FIF
O
error
CD
bit-7
bit-7
bit-15
bit-6
0
RCV
R
trigge
r
(LSB)
0/FIF
Os
enabl
ed
Set
break
0
trans
empt
y
RI
bit-6
bit-6
bit-14
bit-5
0
0
0
Set
parity
0
trans
holdi
ng
empt
y
DSR
bit-5
bit-5
bit-13
bit-4
0
0
0
Even
parity
Loop
back
break
interr
upt
CTS
bit-4
bit-4
bit-12
bit-3
Modem
status
interrup
t
DMA
Mode
select
int
priority
bit-2
Parity
enable
INT
enable
framing
error
delta
CD*
bit-3
bit-3
bit-11
bit-2
Receiv
e line
status
interru
pt
XMITF
IFO
reset
Int
priority
bit-1
Stop
bits
Not
used
parity
error
delta
RI*
bit-2
bit-2
bit-10
DLL and DLM are accessible only when LCR bit-7 is set to “1”.
bit-1
Transmi
t
holding
register
RCVRF
IFO
reset
Int
priority
bit-0
Word
length
bit-1
RTS*
overrun
error
delta
DSR*
bit-1
bit-1
bit-9
bit-0
Receive
holding
register
FIFO
enable
Int
status
Word
length
bit-0
DTR*
receive
data
ready
delta
CTS*
bit-0
bit-0
bit-8
5
408-432-9100/www.impweb.com
© 2002 IMP, Inc.
5 Page 
IMP16C554
19.2K
38.4K
56K
115.2K
6
3
2
1
2.77
IMP16C554 EXTERNAL RESET CONDITION
REGISTER RESET STATE
IER
ISR
LCR
MCR
LSR
IER BIT 0-7=0
ISR BIT-0=1, ISR BIT 1-7=0
LCR BITS 0-7=0
MCR BITS 0-7=0
LSR BITS 0-4=0,
LSR BITS 5-6=1 LSR,BIT
MSR
FCR
7=0
MSR BITS 0-3=0,
MSR BITS 4-7=input signals
FCR BIT 0-7=0
SIGNALS
TX A-D
RTS* A-D
DTR* A-D
RXRDY*
TXRDY*
INT A-D
RESET STATE
High
High
High
High
Low
Three state mode
AC ELECTRICAL CHARACTERISTICS
TA=0 –700C,Vcc= 5.0V±10% unless otherwise specified
Symbol
T1
T2
T3
T8
T9
T12
T13
T14
T15
T16
T17
Tw
T19
T21
T23
T24
T25
Tr
T26
T28
T29
T30
T31
T32
T33
T34
T35
T44
T45
T46
T47
Parameter
Clock high pulse duration
Clock low pulse duration
Clock rise/fall time
Chip select setup time
Chip setup time
Data setup time
Data hold time
IOW* delay from chip select
IOW* strobe width
Chip select hold time from IOW*
Write cycle delay
Write cycle =T15+T17
Data hold time
IOR* delay from chip select
IOR* strobe width
Chip select hold time from LOR*
Read cycle delay
Read cycle =T23+T25
Delay from IOR* to data
Delay from IOW* to output
Delay to set interrupt from MODEM
input
Delay to reset interrupt from IOR*
Delay from stop to set interrupt
Delay from IOR* to reset interrupt
Delay from initial INT reset to transmit
start
Delay from stop to interrupt
Delay from IOW* to reset interrupt
Delay from stop to set RxRdy
Delay from IOR* to reset RxRdy
Delay from IOW* to set TxRdy
Delay from start to reset TxRdy
Limits
Min Typ
20
20
5
0
15
15
10
50
0
55
105
15
10
65
0
55
115
8
Max
10
25
35
50
70
70
1Rck
200
24
100
175
1RCL
K
1
195
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*
ns
ns
us
ns
*
N Baud rate devisor
1 216-1
Conditions
100 pF load
100 pF load
100 pF load
100 pF load
100 pF load
100 pF load
Note 1: = Baudout cycle
11
408-432-9100/www.impweb.com
© 2002 IMP, Inc.
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet IMP16C554.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IMP16C552 | Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port | IMP Inc |
| IMP16C552-CJ68 | Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port | IMP Inc |
| IMP16C552-IJ68 | Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port | IMP Inc |
| IMP16C554 | Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFOs | IMP Inc |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |