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PDF IMP16C552-CJ68 Data sheet ( Hoja de datos )

Número de pieza IMP16C552-CJ68
Descripción Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port
Fabricantes IMP Inc 
Logotipo IMP  Inc Logotipo



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IMP16C552
Data Communications
Dual Universal Asynchronous
Receiver/Transmitter (UART)
. with 16-BYTE FIFO & Parallel Printer Port
Key Features
Two fully programmable serial 1/0
channels (DC TO. 512K BAUD )
Tri-state TTL drive capabilities for
bi-directional data bus and control bus
on each channel
Loopback control for communications
link fault isolation for each UART
Line break generation and detection
for each UART
Complete status reporting capabilities
Generation and stripping of serial
asynchronous data control bits
(start ,stop parity )
Programmable baud rate generator
and modem control signals for each
channel
Pin Configuration
Fully prioritized independent interrupt
system controls for each channel
16byte FIFO buffers on both transmit
and receive of each channel to reduce
number of interrupts presented to the
CPU
Programmable FIFO threshold loves
of 1,4,8,or 14,bytes on each channel
Two modes of DMA signaling
available for transfer of data
characters to and from FIFO buffers
Fully bi-directional
centronics
compatible parallel port direct printer
interface
Advanced CMOS low power
technology with single +5voit supply
68-pin PLCC package
SOUT1
DTR1*
RTS1*
DSR1*
D0
D1
D2
D3
D4
D5
D6
D7
TXRdy0*
VCC
RTS0*
DTR0*
SOUT0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
IMP 16C552
60 DSR*D
59 INT2
58 SLIN*+
57 INIT*+
56 AFD*+
55 STB*+
54 VSS
53 PD0
52 PD1
51 PD2
50 PD3
49 PD4
48 PD5
47 PD6
46 PD7
45 INT0
44 BDO
1
408-432-9100/www.impweb.com
© 2002 IMP, Inc.

1 page




IMP16C552-CJ68 pdf
IMP16C552
Mnemonic Pin Pin#
type
description
RESET
IN
SIN0 STS1 IN
DSR0*,
DSR1*
IN
DSR0*
DSR1*
IN
RLSD0*
RISD1*
IN
RI0* RI1* IN
VCC
VSS
IN
39
41.62
28.13
31.5
29.8
30.6
23.40.64
2.7.27
43.54
Master reset: When this input is low it clears all the register(except the
Receiver Buffer, Transfer Holding and Divisor Latches) and the control
logic of the both channels and parallel port the states of various output
signals are affected by an active RESET input (refer to table 1) .this
input is buffered with a TTL-compatible schmitt trigger with 0.5v
hysteresis.
Serial inputs :Serial data input from the communication link such as
peripheral device , MODE or data set to the associated serial channel
Clear To Send: When low this pin indicates that the MODEM or data
set is ready to exchange data The CTS0(1)*.signal is a MODEM status
input whose conditions can be tested by the CPU reading bit4(CTS)of
the MODEM Status Register Bit4 is the complement of the CTS0(1)
signal Bit 0 (DCTS )of the MODEM status register indicates whether the
CTS(1)* input has changed state since the previous reading of the
modem status register CTS0(1)* has no the Transmitter
Note: whenever the CTS bit of the MODEM status register changes
state an interrupt is generated if the MODEM status interrupt is enabled
Data Set Ready :When low this pin indicates that modem or data set is
ready to establish the communication link with the UART the DSR0(1)
signal is a MODEM status input whose condition can be tested by the
CPU reading bit 5 (DSR)of the MODEM status register bit 5 is the
complement of the DSR0(1)* signal. bit 1 (DDSR) of the MODEM Status
Register Indicates whether the DSR0(1)* input has changed state since
the previous reading of the MODEM Status Register DSR0(1)* has no
the transmitter
Note: Whenever the DSR bit of the MODEM Status Register changes
state, an interrupt is generated if the MODEM status interrupt is enable
Receiver Line Signal Detect: When low ,this pin indicates that the data
canter has been detected by the MODEM or data set The RLSD0(1)*
signal is a MODEM status input whose condition can be tested by the
CPU reading bit 7(RLSD)of the MODEM Status Register Bit 7 is the
complement of the RLSD0(1)* signal. Bit 3 (DRLSD) of the MODEM
Status Register indicates whether the RLSD0(1)* input has changed
state since the previous reading of the MODEM Status Register
RLSD0(1)* has no effect on the receive
Note: whenever the RLSD bit of the MODE status register changes state
on interrupt is generated if the MODEM status interrupt is enable
Ring indicator : when low this pin indicates that a telephone ringing
signal has been received by the MODEM or data set The RI0(1)* signal
is a MODEM status input whose condition can be tested by the CPU
reading bit 6 (RI) of the MODEM Status Register Bit 6 is the
complement of the RI0(1) signal Bit2 (TERI) of MODEM Status
Register indicates whether the RI0(1) input signal has changed from a
low to a high state since the previous reading of the MODEM Status
Register.
Note: whenever the RI bit of the MODEM Status Register changes from
a low to a high state an interrupt is generated if the MODEM status
interrupt is enabled
+5V supply
Ground
5
408-432-9100/www.impweb.com
© 2002 IMP, Inc.

5 Page





IMP16C552-CJ68 arduino
IMP16C552
Table II Accessible IM16c552 Registers for each serial channel
Register address
4
Bit MODEM
no Control
Register
5
Line status
Register
(read only)
6
MODEM
Status
Register
7
Scratch
Pad
Register
0DLAB=1
Divisor
Latch
(LSB)
MCR
0 Data
Terminal
Read
(RTS)
LSR
Data
Ready
(DR)
1 Request to Overrun
send (RTS) Error
(OE)
2 Cut 1
Parity
Error
(PE)
MSR
Delta
Clear to
Send
(DCTS)
Delta
Data set
Ready
(DDSR)
Trailing
Edge Ring
Indicator
(TERI)
SCR
Bit 0
Bit 1
Bit 2
DLL
Bit 0
Bit 1
Bit 2
3 Out 2
(INTE)
4 Loop
Framing
Error
(FE)
Break
Interrupt (BI)
Delta
Receiver
Line
Detect
(DRLSD)
Clear to
Send (CTS)
Bit 3
Bit 4
Bit 3
Bit 4
50
60
Transmitter
Holding
Register
Empty
(THRE)
Transmitter
Empty
(TEMT)
Data Set
Ready
(DSR)
Ring
Indicator
(RI)
70
Error in
RCVR
FIFO(``)
(EIRF)
Receive
Line Signal
Detect
(RLSD)
(*) These bits are read 0 in Character Mode of IMP16C552
Bit 5
Bit 6
Bit 7
Bit 5
Bit 6
Bit 7
1DLAB=1
Divisor
Latch
(MSB)
DLM
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
11
408-432-9100/www.impweb.com
© 2002 IMP, Inc.

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