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PDF IMP1232 Data sheet ( Hoja de datos )

Número de pieza IMP1232
Descripción 5V P Power Suppl er Supply Monit y Monitor and or and Reset Cir eset Circuit
Fabricantes IMP Inc 
Logotipo IMP  Inc Logotipo



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No Preview Available ! IMP1232 Hoja de datos, Descripción, Manual

IMP1232LP/LPS
POWER MANAGEMENT
5V µP Power Supply Monitor and
Reset Circuit
– Selectable Trip-Point Tolerance
and Watchdog Period
– Push-Button Reset
The IMP1232LP/LPS microprocessor supervisor can halt and restart a
“hung-up” or “stalled” microprocessor, restart a microprocessor after a
power failure, and debounce and interface a manual push-button micro-
processor reset switch. The low-power supervisors feature 40% lower
supply current than the pin compatible Dallas Semiconductor
DS1232LP/LPS.
Precision temperature compensated reference and comparator circuits
monitor the 5V, VCC input voltage. During power-up or when the VCC
power supply falls outside selectable tolerance limits, both the RESET
and RESET become active. When VCC rises above the threshold voltage,
the reset signals remain active for an additional 250ms minimum,
allowing the power supply and system microprocessor to stabilize. The
trip point tolerance signal, TOL, selects the trip level tolerance to be
either 5- or 10-percent.
Each device has both a push-pull, active HIGH reset output and an open
drain, active LOW reset output.
A debounced manual reset input activates the reset outputs for a mini-
mum period of 250ms.
Also included is a watchdog timer to stop and restart a microprocessor
that is “hung-up”. Three watchdog time-out periods are selectable:
Key Features
x Pin compatible with the Dallas Semiconductor
DS1232LP/1232LPS
— 40% lower supply current
x 5V supply monitor
x Selectable watchdog period
x Debounce manual push-button reset input
x Precision temperature-compensated voltage
reference and comparator
x Power-up, power-down and brownout detection
x 250ms reset time
x Active LOW open-drain reset and active HIGH
push-pull output
x Selectable trip point tolerance: 5% or 10%
x Low-cost, surface mount packages: 8/16-pin
SO, 8-pin DIP and 8-pin MicroSO
x Wide operating temperature – 40°C to +85°C
(N/EPA suffixed devices)
150ms, 610ms and 1,200ms. If the ST input is not strobed
LOW before the time-out period expires, a reset is issued.
Devices are available in 8-pin DIP, 8/16-pin SO and com-
pact 8-pin MicroSO packages.
Block Diagram
VCC
TOL
8 (15)
3 (6)
5%/10% Tolerance
Selection
IMP1232LP/LPS
(16-Pin Package)
+
Reference
VCC
PBRST
1 (2)
2 (4)
TD
7 (13)
ST
© 1999 IMP, Inc.
40k
Push Button
Debounce
Watchdog
Timebase Selection
Watchdog
Transition Detector
Reset &
Watchdog Timer
4 (8)
GND
408-432-9100/www.impweb.com
6 (11)
RESET
5 (9)
RESET
1232_03.eps
1

1 page




IMP1232 pdf
IMP1232LP/LPS
Application Information
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that is
“hung-up”. Through the time delay input, TD, three watchdog
time-out periods are selectable: 150ms, 610ms and 1,200ms. If the
strobe input, ST, is not strobed LOW prior to timeout, reset signals
become active. On power-up or after the supply voltage returns to
an in-tolerance condition, the reset signal remains active for
250ms minimum, allowing the power supply and system micro-
processor to stabilize.
ST Pulses as short as 20ns can be detected.
Valid
Valid
Invalid
Strobe
Strobe
Strobe
ST
RESET
tRST
tST
tTD
(Min)
tTD
(Max)
A HIGH-to-LOW ST signal transition must be regularly issued
no later than the minimum time-out period defined by the state of
the TD signal. This guarantees the watchdog timer does not
time-out.
Timeouts periods of approximately 150ms, 610ms or 1,200ms are
selected through the TD pin.
TD Voltage Level
Watchdog Time-Out Period (ms)
Min Nominal Max
GND
62.5 150 250
Floating
250 610 1000
VCC
500
1200
2000
1232_t03.eps
The watchdog timer cannot be disabled. It must be strobed with a
high-to-low transition to avoid a watchdog timeout.
Note: ST is ignored whenever a reset is active.
Figure 5. Timing Diagram: Strobe Input
1232_09.eps
5V
IMP1232LP/LPS
1
PBRST
2
TD
8
VCC
7
ST
36
TOL RESET
45
GND RESET
10k
µP
RESET
MREQ
Address
Bus
Figure 6. Application Circuit: Watchdog Timer
Decoder
1232_07.eps
© 1999 IMP, Inc.
408-432-9100/www.impweb.com
5

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