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Número de pieza KT8555J
Descripción TIME SLOT ASSIGNMENT CIRCUIT
Fabricantes Samsung semiconductor 
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KT8555
TIME SLOT ASSIGNMENT CIRCUIT
INTRODUCTION
The KT8555 is a per channel Time Slot Assignment Circuit
(TSAC) that produces 8-bit receive and transmit time slots for
four 1 CHIP CODEC.
Each frame synchronization pulse may be independently
assigned to a time slot in a frame of up to 84 time slots.
20-CERDIP
FEATURES
l Single, 5V operation
l Low power consumption: 5mW
l Controls four 1 CHIP CODEC
l Independent transmit and receive frame syncs
enables
l channel unidirectional mode
l Up to 64 time slots per frame
l Compatible with KT8554/7 CODECs
l TTL and CMOS compatible
PIN CONFIGURATION
ORDERING INFORMATION
Device
Package Operating Temperature
KT8555J 20-CERDIP
- 20°C ~ + 125°C
FSX1 1
FSR1 2
FSX0 3
FSR0 4
TSX 5
DC 6
CLKC 7
CS 8
KT8555
MODE 9
GND 10
20 VCC
19 FSR2
18 FSX2
17 FSR3
16 FSX3
15 CH0
14 CH1
13 RSYC/CH2
12 XSYC
11 BCLK
Fig. 1

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KT8555J pdf
KT8555
TIME SLOT ASSIGNMENT CIRCUIT
APPLICATION CIRCUIT
The KT8555 TSAC combined with any kind of 1 CHIP CODEC from KT8554/7 series can obtain data timing as illustrated
in Fig. 3. Even though FSX output goes high before BCLK gets high, the DX output of the 1 CHIP CODEC remains in the
TRI-STATE mode until both outputs are high. The eight bit period is shortened to avoid PCM data clash at PCM pre-
highway.
Alternatively, full 8 bits can be obtained by inverting the BCLK to the 1 CHIP CODEC devices, thereby rising edges of
BCLK and FSX/R are aligned.
Fig. 4 is typical timing of the control data interface.
Fig. 5 is the typical application circuit at operating control mode 2.
BCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
XSYC
FSX1
FSX2
DX
1 2 3 4 5 6 78
2 3 4 5 6 78
TSX
Fig. 3 Transmit Data Timing
CLKC
CH0, CH1
CS
DC
X R T5 T4 T3 T2 T1 T0
Fig. 4 Control Data Timing
X R T5 T4

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