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Número de pieza | KS9287 | |
Descripción | DIGITAL SIGNAL PROCESSOR | |
Fabricantes | Samsung semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de KS9287 (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
No Preview Available ! DIGITAL SIGNAL PROCESSOR
KS9287
KS9287
PRELIMINARY
DATA SHEET
1999.6.7
1
1 page DIGITAL SIGNAL PROCESSOR
PIN DESCRIPTION
No. Pin Name I/O
Description
1
VDDA
- Analog VDD
2
DPDO
O Charge pump output for Digital PLL
3
DPFIN
I Filter input for Digital PLL
4
DPFOUT
O Filter output for Digital PLL
5
CNTVOL
I VCO control voltage for Digital PLL
6
VSSA
- Analog Ground
7
DATX
O Digital Audio Serial Output
8 XIN I X'tal oscillator input
9
XOUT
O X'tal oscillator output
10
WDCH
O Word clock output of 48 bits/Slot (88.2 kHz)
11
LRCH
O Channel clock output of 48 bits/Slot (44.1 kHz)
12
SADT
O Serial audio data output of 48 bits/Slot (MSB first)
13 VSS - Digital Ground
14
BCK
O Bit clock output of 48 bits/Slot (2.1168 MHz)
15
C2PO
O C2 Pointer for Serial audio data
16
TIM2
O Normal or Double speed control output
17 EFMFLAG O 8 to14 demodulation error flag
18 UDTFLAG O Undesiable T Flag (Lower 3T signal in EFM signal)
19
FSYNC
O Detected Frame Sync
20
EFMZ
O EFM signal demodulated NRZI
21
V34M
O Internal VCO clock (34.5744MHz)
22 TEST0 I Test input (H: Test, L: Normal)
23 RBCK I Read base clock
24
EMPH
O Emphasis output (H: Emphasis On, L: Emphasis Off)
25
LKFS
O The Lock Status output of frame sync
26
S0S1
O Output of subcode sync signal (S0+S1)
27 RESET I System reset at "L"
28 SQEN I SQCK control signal (H: External clock, L: Internal clock)
29
SQCK
I/O Subcode-Q data bit clock
30
SQDT
O Serial output of Subcode-Q data
31
SQOK
O The CRC check result signal output of Subcode-Q
32 SBCK I Subcode data bit clock
KS9287
5
5 Page DIGITAL SIGNAL PROCESSOR
KS9287
FUNCTIONAL DESCRIPTION
MICOM INTERFACE
Data input from MICOM is received in MDAT, and transmitted by MCK. This signal is stored in the Control Register
by MLT. The Timing diagram for this process is shown in Figure 1
.
MDAT
D0 D1 D2 D3 D4 D5 D6 D7 <MSB>
MCK
MLT
Register
(9X ~ FX)
Valid
MDAT
MCK
MLT
Register
(88XX ~ 8DXX)
D0 D1 D2 D3 D4
¡ó D11 D12 D13 D14 D15 <MSB>
¡ó
Figure 1. MICOM Data Input Timing Diagam
Valid
Register
Name
CNTL-Z Data control
CNTL-S
CNTL-L
CNTL-U
CNTL-W
Frame sync protect,
attenuation control
Tracking counter
(lower)
Tracking counter
(upper)
CLV control
CNTL-C CLV-mode
CNTL-D Double-speed
Table 1. Control Register and Data
Address
D7~D4
1001
(9X)
1010
(AX)
1011
(BX)
1100
(CX)
1101
(DX)
1110
(EX)
1111
(FX)
D3
ZCMT
FSEM
TRC3
TRC7
-
-
Data
D2 D1
HIPD
NCLV
FSEL
WSEL
TRC2
TRC1
TRC6
TRC5
WB WP
CLV MODE
- DS1
D0
CRCQ
/ISTAT
Pin
HI-Z
ATTM
HI-Z
TRC0 /complete
TRC4
/count
GAIN
HI-Z
/(Pw ≥ 64)
DS2 HI-Z
11
11 Page |
Páginas | Total 29 Páginas | |
PDF Descargar | [ Datasheet KS9287.PDF ] |
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