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PDF KS9286B Data sheet ( Hoja de datos )

Número de pieza KS9286B
Descripción DIGITAL SIGNAL PROCESSOR for CDP
Fabricantes Samsung semiconductor 
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No Preview Available ! KS9286B Hoja de datos, Descripción, Manual

KS9286B/KS9286B-L
DIGITAL SIGNAL PROCESSOR for CDP
DIGITAL SIGNAL PROCESSOR
The KS9286B is a CMOS integrated circuit designed for
the Digital Audio Signal Processor for Compact Disc
Player. It is a monolithic IC that builts-in 16-bit Digital
Analog Convertor, ESP Interface and Digital De-emphasis
additional conventional DSP function.
80-QFP-1420C
FEATURES
• EFM data demodulation
• Frame sync detection/protection/insertion
• Powerful error correction (C1: 2error, C2: 4erasure)
• Interpolation
• 8fs digital filter (51th+13th+9th)
• Subcode data serial output
• CLV servo controller
• Micom interface
• Digital audio output
• Digital de-emphasis
• ESP interface
• Built-in 16K SRAM
• Built-in Digital PLL
• Double speed play available
• Built-in 16-bit D/A converter
• Operating Voltage range
KS9286B : 5V
KS9286B-L : 3.4V
ORDERING INFORMATION
Device
Package
KS9286B
80-QFP-1420C
KS9286B-L
Tempe. Range
-20oC ~ +75oC
1

1 page




KS9286B pdf
KS9286B/KS9286B-L
DIGITAL SIGNAL PROCESSOR for CDP
PIN DESCRIPTION (continued)
PIN NO SYMBOL IO
DESCRIPTION
30
SQDT
O Serial output of Subcode-Q data
31
SQOK
O The CRC (Cycle Redundancy Check) check result signal output of Subcode-Q
32 SBCK I Clock for output subcode data
33
SDAT
O Subcode serial data output
34 DVDD1 - Digital VDD1
35 MUTE I Mute control input ("H": Mute ON)
36 MLT I Latch Signal Input from Micom (Schmit Trigger)
37 MDAT I Serial data input from Micom (Schmit Trigger)
38 MCK I Serial clock input from Micom (Schmit Trigger)
39
RD7
I/O SRAM data I/O port 8 (MSB)
40
RD6
I/O SRAM data I/O port 7
41
RD5
I/O SRAM data I/O port 6
42
RD4
I/O SRAM data I/O port 5
43
RD3
I/O SRAM data I/O port 4
44
RD2
I/O SRAM data I/O port 3
45
RD1
I/O SRAM data I/O port 2
46
RD0
I/O SRAM data I/O port 1 (LSB)
47
FLAG1
I/O Monitoring output for error correction (RA0)
48
FLAG2
I/O Monitoring output for error correction (RA1)
49
FLAG3
I/O Monitoring output for error correction (RA2)
50
FLAG4
I/O Monitoring output for error correction (RA3)
51
FLAG5
I/O Monitoring output for error correction (RA4)
52
/PBCK
I/O Output of VCO/2 (4.3218MHz) (RA5)
53
DVSS2
I/O Digital ground 2
54
FSDW
I/O Window or unprotected frame sync (RA6)
55
ULKFS
I/O Frame sync protection state (RA7)
56 /JIT I/O Display of either RAM overflow or underflow for + 4 frame jitter margin (RA8)
57
C4M
I/O Only monitoring signal (4.2336MHz) (RA9)
58
C16M
I/O 16.9344MHz signal output(RA10)
59 /WE I/O Terminal for test
60 /CS I/O Terminal for test
5

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KS9286B arduino
KS9286B/KS9286B-L
DIGITAL SIGNAL PROCESSOR for CDP
1) CNTL-Z REGISTER
It is a register to control zero cross mute of audio data, phase terminal
control, phase servo control and having or not of CRCF in data SQDT.
ZCMT
-
NCLV
CRCQ
DATA = 0
D3 Zero cross mute is OFF
D2 -
D1 The phase servo is acted by frame sync
D0 SQDT outputs except for SQOK
DATA = 1
Zero cross mute is ON
-
The phase servo is controlled by base
counter
SQDT=CRCF when S0S1='H'
Table 2. CNTL-Z register & data
2) CNTL-S REGISTER
It is a register to control frame sync protection and attenuation.
FSEM
0
0
1
1
FSEL
0
1
0
1
FRAME
2
4
8
13
WSEL
0
1
CLOCK
+3
+7
ATTM
0
0
1
1
Table 3. CNTL-S register & data
3) CNTL-L, U REGISTER
After the counter of track that must be counted is inputted from Micom, the data
is loaded to tracking counter by CNTL-L, U register.
MUTE
0
1
0
1
dB
0
-
-12
-12
11

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