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PDF KM48C8004B Data sheet ( Hoja de datos )

Número de pieza KM48C8004B
Descripción 8M x 8bit CMOS Dynamic RAM with Extended Data Out
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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KM48C8004B, KM48C8104B
CMOS DRAM
8M x 8bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), package type (SOJ or TSOP-
II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities.
This 8Mx8 EDO Mode DRAM family is fabricated using Samsungs advanced CMOS process to realize high band-width, low power con-
sumption and high reliability.
FEATURES
• Part Identification
- KM48C8004B(5.0V, 8K Ref.)
- KM48C8104B(5.0V, 4K Ref.)
Active Power Dissipation
Speed
-45
-5
-6
Refresh Cycles
8K
550
495
440
Unit : mW
4K
715
660
605
Part
NO.
KM48C8004B*
KM48C8104B
Refresh
cycle
8K
4K
Refresh time
Normal
64ms
* Access mode & RAS only refresh mode
: 8K cycle/64ms
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms
Performance Range
Speed tRAC
tCAC
-45 45ns 12ns
-5 50ns 13ns
-6 60ns 15ns
tRC
74ns
84ns
104ns
tHPC
17ns
20ns
25ns
• Extended Data Out Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• TTL(5.0V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +5.0V±10% power supply
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
Control
Clocks
VBB Generator
Vcc
Vss
Refresh Timer
Refresh Control
Refresh Counter
A0~A12
(A0~A11)*1
A0~A9
(A0~A10)*1
Row Address Buffer
Col. Address Buffer
Note) *1 : 4K Refresh
Row Decoder
Memory Array
8,388,608 x 8
Cells
Column Decoder
Data in
Buffer
Data out
Buffer
DQ0
to
DQ7
OE
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

1 page




KM48C8004B pdf
KM48C8004B, KM48C8104B
CAPACITANCE (TA=25°C, VCC=5.0V, f=1MHz)
Parameter
Symbol
Input capacitance [A0 ~ A12]
CIN1
Input capacitance [RAS, CAS, W, OE]
CIN2
Output capacitance [DQ0 - DQ7]
CDQ
Min
-
-
-
CMOS DRAM
Max Units
5 pF
7 pF
7 pF
AC CHARACTERISTICS (0°CTA70°C, See note 1,2)
Test condition : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V
Parameter
Symbol
-45
Min Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay from CAS
OE to output in Low-Z
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
tRC
tRWC
tRAC
tCAC
tAA
tCLZ
tCEZ
tOLZ
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
74
101
45
12
23
3
3 13
3
1 50
25
45 10K
8
35
7 5K
11 33
9 22
5
0
7
0
7
23
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
tRCS
tRCH
tRRH
tWCH
tWP
tRWL
tCWL
tDS
0
0
0
7
6
8
7
0
-5
Min Max
84
113
50
13
25
3
3 13
3
1 50
30
50 10K
8
38
8 10K
11 37
9 25
5
0
7
0
7
25
0
0
0
7
7
8
7
0
-6
Min Max
104
138
60
15
30
3
3 13
3
1 50
40
60 10K
10
40
10 10K
14 45
12 30
5
0
10
0
10
30
0
0
0
10
10
10
10
0
Units Note
ns
ns
ns 3,4,10
ns 3,4,5
ns 3,10
ns 3
ns 6,14
ns 3
ns 2
ns
ns
ns
ns
ns
ns 4
ns 10
ns
ns
ns
ns
ns
ns
ns 8
ns 8
ns
ns
ns
ns
ns
ns 9

5 Page





KM48C8004B arduino
KM48C8004B, KM48C8104B
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
VIH -
RAS
VIL -
VIH -
CAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ3(7)
VIH -
VIL -
tRAS
tRC
tCRP
tRCD
tRAD
tASR
tRAH
ROW
ADDRESS
tASC
tCSH
tRSH
tCAS
tRAL
tCAH
COLUMN
ADDRESS
tCWL
tRWL
tWP
tOED
tDS
tOEH
tDH
DATA-IN
CMOS DRAM
tRP
tCRP
Dont care
Undefined

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