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PDF KM44S32030 Data sheet ( Hoja de datos )

Número de pieza KM44S32030
Descripción 8M x 4Bit x 4 Banks Synchronous DRAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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KM44S32030
8M x 4Bit x 4 Banks Synchronous DRAM
Preliminary
CMOS SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS Latency (2 & 3)
-. Burst Length (1, 2, 4, 8)
-. Burst Type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst Read Single-bit Write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The KM44S32030 is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits,
fabricated with SAMSUNGs high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clcok
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
ORDERING INFORMATION
Part NO.
KM44S32030T-G/F8
KM44S32030T-G/FH
KM44S32030T-G/FL
KM44S32030T-G/F10
MAX Freq.
125MHz
100MHz
100MHz
100MHz
Interface Package
LVTTL
54pin
TSOP(II)
Data Input Register
Bank Select
CLK
ADD
8M x 4
8M x 4
8M x 4
8M x 4
Column Decoder
LCKE
LRAS
LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
LWE
LDQM
DQi
LDQM
CLK
CKE
CS
RAS
CAS
WE DQM
* Samsung Electronics reserves the right to
change products or specification without
notice.
REV. 2 Mar. '98

1 page




KM44S32030 pdf
KM44S32030
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4 / 0.4
1.4
tr / tf = 1 / 1
1.4
See Fig. 2
3.3V
Output
870
1200
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Preliminary
CMOS SDRAM
Unit
V
V
ns
V
Z0=50
Vtt=1.4V
50
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
tRRD(min)
RAS to CAS delay
tRCD(min)
Row precharge time
tRP(min)
Row active time
tRAS(min)
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to new col. address delay
tCDL(min)
Last data in to burst stop
tBDL(min)
Col. address to col. address delay
tCCD(min)
Number of valid
output data
CAS latency=3
CAS latency=2
-8
16
20
20
48
68
8
Version
-H -L
20 20
20 20
20 20
50 50
100
70 70
10 10
1
1
1
2
1
Unit
-10
20 ns
24 ns
24 ns
50 ns
us
80 ns
12 ns
CLK
CLK
CLK
ea
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Note
1
1
1
1
1
2
2
2
3
4
REV. 2 Mar. '98

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