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PDF KM44C4105C Data sheet ( Hoja de datos )
| Número de pieza | KM44C4105C | |
| Descripción | 4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out | |
| Fabricantes | Samsung semiconductor | |
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KM44C4005C, KM44C4105C
CMOS DRAM
4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out
DESCRIPTION
This is a family of 4,194,304 x 4 bit Quad CAS with Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high
speed random access of memory cells within the same row, so called Hyper Page Mode. Refresh cycle (2K Ref. or 4K Ref.), access
time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of
this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is avail-
able in L-version. Four separate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode.
This 4Mx4 Extended Data Out Quad CAS DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-
width, low power consumption and high reliability.
FEATURES
• Part Identification
- KM44C4005C/C-L (5V, 4K Ref.)
- KM44C4105C/C-L (5V, 2K Ref.)
• Active Power Dissipation
Unit : mW
Speed
Refresh Cycle
4K 2K
-5 495
605
-6 440
550
• Extended Data Out mode operation
(Fast Page Mode with Extended Data Out)
• Four separate CAS pins provide for separate I/O operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• TTL compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply
• Refresh Cycles
Part Refresh
NO. cycle
C4005C
C4105C
4K
2K
Refresh period
Normal
L-ver
64ms
32ms
128ms
• Performance Range
Speed tRAC
tCAC
-5 50ns 13ns
-6 60ns 15ns
tRC
84ns
104ns
tHPC
20ns
25ns
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS0 - 3
W
A0-A11
(A0 - A10) *1
A0 - A9
(A0 - A10) *1
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Memory Array
4,194,304 x 4
Cells
Column Decoder
Vcc
Vss
Data in
Buffer
DQ0
to
DQ3
Data out
Buffer
OE
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
1 page  
KM44C4005C, KM44C4105C
CAPACITANCE (TA=25°C, VCC=5V, f=1MHz)
Parameter
Input capacitance [A0 ~ A11]
Input capacitance [RAS, CASx, W, OE]
Output capacitance [DQ0 - DQ3]
Symbol
CIN1
CIN2
CDQ
Min
-
-
-
CMOS DRAM
Max
5
7
7
Units
pF
pF
pF
AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)
Test condition : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V
Parameter
Symbol
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay from CAS
OE to output in Low-Z
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
tRC
tRWC
tRAC
tCAC
tAA
tCLZ
tCEZ
tOLZ
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
tRWL
tCWL
-5
Min Max
84
106
50
13
25
3
3 13
3
2 50
30
50 10K
13
38
8 10K
20 37
15 25
5
0
10
0
8
25
0
0
0
10
10
13
8
-6
Min Max
104
140
60
15
30
3
3 15
3
2 50
40
60 10K
15
45
10 10K
20 45
15 30
5
0
10
0
10
30
0
0
0
10
10
15
10
Units Notes
ns
ns
ns 3,4,10
ns 3,4,5,20
ns 3,10
ns 3,20
ns 6,13
ns 3
ns 2
ns
ns
ns 16
ns 19
ns 25
ns 4,18
ns 10
ns 17
ns
ns
ns 18
ns 18
ns
ns
ns 8,17
ns 8
ns 16
ns
ns
ns 19
5 Page 
KM44C4005C, KM44C4105C
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
VIH -
RAS
VIL -
VIH -
CAS0
VIL -
VIH -
CAS1
VIL -
VIH -
CAS2
VIL -
VIH -
CAS3
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ3
VIH -
VIL -
tCRP
tCRP
tRCD
tRAS
tRC
tCSH
tRSH
tCAS
tCRP
tCRP
tCLCH
tASR
tRAD
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tRAL
tCWL
tRWL
tWP
tOED
tOEH
tDS tDH
DATA-IN
CMOS DRAM
tRP
tCRP
Don′t care
Undefined
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet KM44C4105C.PDF ] | |
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