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PDF KM44C1000D Data sheet ( Hoja de datos )

Número de pieza KM44C1000D
Descripción 1M x 4Bit CMOS Dynamic RAM with Fast Page Mode
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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KM44C1000D, KM44V1000D
CMOS DRAM
1M x 4Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 1,048,576 x 4bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5V or +3.3V), access time (-5, -6 or -7), power consumption(Normal or Low power), and
package type (SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and
Hidden refresh capabilities. Furthermore, self-refresh operation is available in 3.3V Low power version.
This 1Mx4 Fast Page Mode DRAM family is fabricated using Samsungs advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as main memory for main frames and mini computers, personal computer and high per-
formance microprocessor systems.
FEATURES
• Part Identification
- KM44C1000D/D-L(5V, 1K Ref.)
- KM44V1000D/D-L(3.3V, 1K Ref.)
Active Power Dissipation
Speed
-5
-6
-7
3.3V
-
220
200
Unit : mW
5V
470
415
360
Refresh Cycles
Part Refresh
NO. cycle
KM44C1000D
KM44V1000D
1K
Refresh Period
Normal L-ver
16ms 128ms
Performance Range
Speed tRAC tCAC tRC
-5 50ns 15ns 90ns
-6 60ns 15ns 110n
-7 70ns 20ns 130n
tPC
35ns
40ns
45ns
Remark
5V only
5V/3.3V
5V/3.3V
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (3.3V, L-ver only)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early write or output enable controlled write
• JEDEC Standard pinout
• Available in 26(20)-pin SOJ 300mil and TSOP(II)
300mil packages
• Single +5V±10% power supply(5V product)
• Single +3.3V±0.3V power supply(3.3V product)
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
Control
Clocks
VBB Generator
Vcc
Vss
A0~A9
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Memory Array
1,048,576 x4
Cells
Column Decoder
Data in
Buffer
DQ0
to
DQ3
Data out
Buffer
OE
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

1 page




KM44C1000D pdf
KM44C1000D, KM44V1000D
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter
Symbol
Input capacitance [A0 ~ A9]
CIN1
Input capacitance [RAS, CAS, W, OE]
CIN2
Output capacitance [DQ0 - DQ3]
CDQ
Min
-
-
-
CMOS DRAM
Max Units
5 pF
7 pF
7 pF
AC CHARACTERISTICS (0°CT70°C, See note 1,2)
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter
Symbol
-5*1
Min Max
-6
Min Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Note) *1 : 5V only
tRC
tRWC
tRAC
tCAC
tAA
tCLZ
tOFF
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
tRWL
tCWL
90 110
132 152
50 60
15 15
25 30
00
0 12 0 12
3 50 3 50
30 40
50 10K 60 10K
15 15
50 60
15 10K 15 10K
20 35 20 45
15 25 15 30
55
00
10 10
00
10 10
25 30
00
00
00
10 10
10 10
15 15
13 15
7
Min Max
130
177
70
20
35
0
0 17
3 50
50
70 10K
20
70
20 10K
20 50
15 35
5
0
10
0
15
35
0
0
0
15
15
15
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
3,4,10
3,4,5
3,10
3
6
2
4
10
8

5 Page





KM44C1000D arduino
KM44C1000D, KM44V1000D
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
VIH -
RAS
VIL -
VIH -
CAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ3(7)
VIH -
VIL -
tRAS
tRC
tCRP
tRCD
tASR
tRAD
tRAH
tASC
ROW
ADDRESS
tCSH
tRSH
tCAS
tCAH
COLUMN
ADDRESS
tRAL
tCWL
tRWL
tWP
tOED
tOEH
tDS tDH
DATA-IN
CMOS DRAM
tRP
tCRP
Dont care
Undefined

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