|
|
PDF KM41V4000D Data sheet ( Hoja de datos )
| Número de pieza | KM41V4000D | |
| Descripción | 4M x 1Bit CMOS Dynamic RAM with Fast Page Mode | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de KM41V4000D (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
KM41C4000D, KM41V4000D
CMOS DRAM
4M x 1Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 4,194,304 x 1bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5V or +3.3V), access time (-5, -6 or -7), power consumption(Normal or Low power), and
package type (SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and
Hidden refresh capabilities. Furthermore, self-refresh operation is available in Low power version.
This 4Mx1 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as main memory for main frames and mini computers, personal computer and high per-
formance microprocessor systems.
FEATURES
• Part Identification
- KM41C4000D/D-L(5V, 1K Ref.)
- KM41V4000D/D-L(3.3V, 1K Ref.)
• Active Power Dissipation
Speed
-5
-6
-7
3.3V
-
220
200
Unit : mW
5V
470
415
360
• Refresh Cycles
Part Refresh
NO. cycle
KM41C4000D
KM41V4000D
1K
Refresh Period
Normal L-ver
16ms 128ms
• Performance Range
Speed tRAC tCAC tRC tPC
-5 50ns 15ns 90ns 35ns
-6 60ns 15ns 110ns 40ns
-7 70ns 20ns 130ns 45ns
Remark
5V only
5V/3.3V
5V/3.3V
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (3.3V, L-ver only)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Common I/O using early write
• JEDEC Standard pinout
• Available in 26(20)-pin SOJ 300mil and TSOP(II)
300mil packages
• +5V±10% power supply(5V product)
• +3.3V±0.3V power supply(3.3V product)
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
Control
Clocks
VBB Generator
Vcc
Vss
A0~A9
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Memory Array
4,194,304 x1
Cells
Column Decoder
Data in
Buffer
D
Data out
Buffer
Q
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
1 page  
KM41C4000D, KM41V4000D
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter
Symbol
Input capacitance [D]
CIN1
Input capacitance [A0 ~ A10]
CIN2
Input capacitance [RAS, CAS, W]
CIN3
Output capacitance [Q]
COUT
Min
-
-
-
-
AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter
Symbol
-5*1
Min Max
-6
Min Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
tRC
tRWC
tRAC
tCAC
tAA
tCLZ
tOFF
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
90 110
110 130
50 60
15 15
25 30
00
0 12 0 12
3 50 3 50
30 40
50 10K 60 10K
15 15
50 60
15 10K 15 10K
20 35 20 45
15 25 15 30
55
00
10 10
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
tRWL
tCWL
0
10
25
0
0
0
10
10
15
13
0
10
30
0
0
0
10
10
15
15
Note) *1 : 5V only
Max
5
5
7
7
7
Min Max
130
150
70
20
35
0
0 17
3 50
50
70 10K
20
70
20 10K
20 50
15 35
5
0
10
0
15
35
0
0
0
15
15
15
15
Units
pF
pF
pF
pF
Units Notes
ns
ns
ns 3,4,10
ns 3,4,5
ns 3,10
ns 3
ns 6
ns 2
ns
ns
ns
ns
ns
ns 4
ns 10
ns
ns
ns
ns
ns
ns
ns
ns 8
ns 8
ns
ns
ns
ns
5 Page 
KM41C4000D, KM41V4000D
READ-WRITE / READ - MODIFY - WRTIE CYCLE
CMOS DRAM
VIH -
RAS
VIL -
VIH -
CAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
D
VIL -
VIH -
Q
VIL -
tRWC
tRAS
tRP
tCRP
tRCD
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDR
COLUMN
ADDRESS
tRSH
tCAS
tCSH
tAWD
tCWD
tRWL
tCWL
tWP
tDS tDH
DATA-IN
tCLZ
tCAC
tAA
tRAC
tOFF
DATA-OUT
Don′t care
Undefined
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet KM41V4000D.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| KM41V4000D | 4M x 1Bit CMOS Dynamic RAM with Fast Page Mode | Samsung semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |